搜索资源列表
CRC校验参考设计_xilinx_verilog
- IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
reg_comp
- 4X4 KEYPAD 的密码比较模块，可以核对6位的密码-4x4 KEYPAD password comparison module, can check the password 6
crc_verilog_xilinx
- CRC校验码，用于对数据流进行crc校验。 主要有CRC_16,CRC_8,CRC_32校验。 所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL.
crc_16
- 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
crc3321
- CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthe
wave_gen
- 波形发生器，带TESTBENCH， 多平台 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn -waveform generator, with TESTBENCH.
Shifters_vhdl
- -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shift
8-CPU
- 简单的8位CPU，内含PDF文件.可自己查看详细说明-simple eight CPU, containing PDF files. They can check details
crc_32_16
- crc校验功能，用硬件语言实现，vhdl或者verilog实现。逻辑功能。-crc check function, hardware language, verilog or vhdl achieve. Logic function.
循环冗余校验码
- 循环冗余校验码(试验报告)-Cyclic Redundancy Check (pilot reports)
sin_cos_rom
- 9bit、512个数据点（1/4周期）的正弦余弦ROM查值表-9bit, 512 data points (1/4 cycle) check the value of the sine and cosine table ROM
usb_phy.tar
- Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check f
CRC10
- CRC校验 自己编写的程序，通过matlab仿真-CRC check
tlk1221jiaoyan_k
- 采用8B/10B编码方式，以不同的模式插入K28.5码进行数据校验，验证tlk1221芯片的数据传输是否正确，观察收发数据是否一致。-To check the data which is transceived by the way of 8B/10B coder/decoder by asserting K28.5 code in different mode and to observe that whether these data have been missed in the tran
checkoutthedate
- 该程序的功能是用来查询日期或是知道日期查询星期几的；-The program' s function is used to check the date or the date of check to know a few of weeks
sequence-check
- 设计一个有限状态机，用以检测输入序列“1110010”-sequence check
STATE-CHECK
- 设计一个有限状态机，用以检测输入序列“1110010”-state check
PARITY-CHECK
- this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check
Vrilog-hdl--Sequence-check.doc
- 用VrilogHDL编写的一个序列检测器-use rilogHDL define a Sequence check Instrument