xilinx timing constrain file

对FPGA的IO口的时序分析小结，能够详细理解其约束时序规则-FPGA timing analysis summary of IO port, capable of a detailed understanding of its timing constraint rules

方法能够自动地约束 PLL 的输入和输出时钟。ALTPLL megafunction 中指定的所有 PLL 参数都用于约束 PLL 的输入和输出时钟。(Methods can automatically constrain PLL input and output clock.Named in ALTPLL megafunction.All PLL parameters are used to constrain PLL input and output clocks.)