搜索资源列表
Based-on-FPGA-of-FIR-filters
- 基于FPGA的高阶FIR滤波器的设计,数字滤波器,分布式算法,CSD编码-Based on FPGA order FIR filters
FPGA-basedmultipliersCSDcode
- 基于FPGA的CSD编码乘法器(在MATLAB环境中)-FPGA-based multipliers CSD code (in MATLAB environment)
FPGArealiztionofdigitalsignalprocessing
- 数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量(canonical signed digit ,CSD)表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHD
filter1
- 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
20FIRfilterwithCSD
- 20阶FIR滤波器,用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters
20FIRFilterDecimal
- 20阶FIR数字滤波器,参数没有进行倍数扩大,参数经过CSD编码处理-20-order FIR digital filter, the parameter no multiple expansion, parameter encoding process after CSD
CSDmultiplier
- Code for CSD Multiplier
fir25
- 用VDHL写的25阶对称FIR滤波器,在塞克隆3FPGA下验证没有问题(AD采样时钟50Mhz,这个对硬件设计有点要求),里面调用官方乘法器API,要节省资源可以采用CSD编码转换乘法器,可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit
fir_csd
- vdhl实现FIR,乘法器采用CSD编码,在资源紧张情况下,可省去很多资源-vdhl achieve FIR, multiplier using CSD coding, in the case of resource constraints, can save a lot of resources