搜索资源列表
LCD显示实验
- ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
dfgg
- 请先删除编译后的debug/release目录以减少压缩包大小-compiled the debug / release directory to reduce the size of compressed
VHDL_交通灯系统
- 用VHDL语言编写，在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2
dynamic_display
- 4 digital LED dynamic display的Verilog HDL源代码，它能动态的显示4位数，为FPGA 的DEBUG 提供便利，非常经典，简单易懂，并且经过了Modelsim/ISE/FPGA(XC3S250ETQ144)验证和实现，好的行为模型就应该大家分享。
IT51_src.tar
- 這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ-This is the latest version of the amendment after 8051, after debug and achieve a certain company's intention on silicon
TASK51_DE0
- FPGA内嵌51核，已通过调试及下载验证。-FPGA embedded 51-core, debug and download validation.
pcicard.rar
- pci debug card 的VHDL源代码,pci debug card of the VHDL source code
实现PS/2接口与RS-232接口的数据传输
- 实现PS/2接口与RS-232接口的数据传输， 可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。,The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received ch
debussy
- Debussy 是NOVAS Software, Inc(思源科技)发展的HDL Debug & Analysis tool，这套软体主要不是用来跑模拟或看波形，它最强大的功能是：能够在HDL source code、schematic diagram、waveform、state bubble diagram之间，即时做trace，协助工程师debug。 本文主要是介绍Debussy的使用，以及如何在Modelsim环境下生成Debussy所需要的fsdb文件-user guide f
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
SignalTap-shiyong
- fpga读写sram（61LV25616），程序附详细注释，包含波形仿真文件及signaltap在线调试文件，并附有文档对程序及signaltap的使用进行了详细说明。 -fpga read and write sram (61LV25616), with detailed program notes, including documents and signaltap waveform simulation debug files online, along with documentatio
vhdl语言实现的16乘16的点阵显示设计代码
- vhdl语言实现的16乘16的点阵显示设计代码，调试通过，可借鉴-VHDL language to achieve the 16 by 16 dot matrix display design code, debug is passed, can learn from-vhdl language implementation of the 16 by 16 dot matrix display design code, debug through, we may learn-VHDL langu
nlint-user-manual nlint verilog vhdl 规则库
- nlint verilog vhdl 规则库 支持自定义 批量检查代码中bug -nlint a eda debug tool software rules ， user define rules ， verify code automatic
jtag
- verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
FPGA-design-and-debug-
- FPGA的设计与调试(专家技术演讲稿免费下载)-FPGA design and debug (expert technical presentations for free download)
FPGA-Debug-Reference-Manual
- FPGA调试基础知识，中文版应用指南，简化Xilinx和Altera FPGA调试过程-FPGA Debug Reference Manual
debug
- 基于LEON3的片上网络调试系统和相关的技术资料-The LEON3 the network on chip debug system and related technical information
FPGA-design-and-debug
- 系统分析了当下的FPGA的设计和调试环节，有一定的参考价值-System analysis of current FPGA design and debug link, there is a certain reference value
DM9000-debug
- DM9000调试教程，对DM9000的调试有一定帮助。-DM9000 debugging tutorial for DM9000 debug some help.