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cpu_vh
- 一个大学计算机组成原理CPU的课程设计，比一般的CPU的课程设计多了几种寻址方式，总共六种寻址方式，对CPU的内部问题能有很深的了解。-Principles of Computer CPU of a university curriculum design, the CPU than the average of several courses designed to address multi-mode, a total of six addressing modes, the CPU'
Fpga4fun
- 从浅到深的FPGA学习小制作，从国外网站上下载的-To learn small production from shallow to deep FPGA downloaded from foreign sites.
VHDLGuideAndCode
- 该教程比较详细的介绍了VHDL语言，对其语法的使用，编程中的技巧由浅到深的进行介绍，并且给出了90个VHDL源代码，其中包括测试程序、各功能测试代码等。由于文档为pdg格式，在PDG Reader文件夹中给出该阅读器。-The tutorial more detailed introduction to the VHDL language, its syntax, the use of programming techniques from shallow to deep, are introd
bios
- 系统BIOS的VHDL设计与实现，可在FPGA上验证，对小型系统的可靠性有深刻的认识。-System BIOS Design and Implementation of VHDL, the FPGA can be verified, for small systems have a deep understanding of reliability.
200986014737910
- 很常用的VHDL例子，能够很深刻的去理解VHDL语言，新手可以很快入门。-VHDL is very commonly used examples can be very deep to understand the VHDL language, novice can be quickly started.
s3esk_startup
- 利用kcpsm3控制lcd显示 平台：ise 10.1， picoblaze， Spartan3e 开发板 说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
WFIFO-32fifo20070821
- 具有32字节深度的FIFO的SPI通信站。-With 32-byte deep FIFO, SPI communication station.
VLSI
- [電子書籍]利用verilog硬體程式語言來設計大型積體電路的經典書籍 "Digital VLSI Design with Verilog" 由淺入深值得一看 -[E-books] verilog hardware descr iption language used to design large-scale integrated circuit classic books " Digital VLSI Design with Verilog" Deep and worth
fifo89
- 先进先出FIFO缓冲器，8位字宽，9位字深，很简易的缓冲器。-FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Embedded_Design_Programming
- This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of
135classic_example_of_Verilog_design
- Verilog的135个经典设计实例，由简到繁，由浅入深，值得收藏！-Verilog' s 135 classic design example, from simple to complex, Deep and worth collecting!
ASIC
- 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从 设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of sy
FPGA
- 华清远见的《FPGA应用开发入门与典型应用》，是超星版本的，里面对FPGA的设计由浅入深，值得一看。-China Qingyuan, see the " FPGA Application Development and Typical Applications" , is the Superstar version, the inside of the FPGA design Deep and worth a visit.
VHDLcode
- 大量VHDL程序，由浅入深包括基础程序，各种接口实验，PC、USB SRAM等扩展板实验，及综合实验设计等。-A large number of VHDL program, Deep and includes basic procedures, various interface experiment, PC, USB' SRAM other expansion board experiments, and the comprehensive experimental design.
NIOS_II
- 国内最好的最简单的介绍NIOS 的东西，由浅入深，不错-Domestic best introduction to the most simple things NIOS, Deep and well
CUDA-CPU-GPU
- 跟大家深入到CUDA的内部，为大家诠释为什么说：唯有NVIDIA CUDA才是终极的CPU-CUDA with you deep into the interior, as we interpret why: Only the CPU is the ultimate NVIDIA CUDA
beijingdaxue_verilog_pdf
- 北大的verilogHDL教程，从潜入深，逐步深入的讲解，但是许多重点都被提到了，是不错的教程。-Peking University verilogHDL tutorial from dive deep, and gradually in-depth explanations, but many have been referred to the focus, is a good tutorial.
buffer
- 一个串行接收，并行发送的缓存器，其数据存储使用双端口SRAM（一读一写）实现，SRAM大小为深64、宽32位（64字×32位，使用提供的双端口SRAM见目录rf2shd4）。缓存器按一位串行输入接收数据，缓存器位置全满后不再接收串行数据输入；并根据读数请求，按接收数据的顺序，将接收完整的32位数据发送出去，并标记该缓存器位置为空，又可以放置新的串行输入数据。 设计了同步和异步两种串行发送方法。-Receive a serial, parallel send buffer, the data
counter
- 这是一个0~9999的计数器，间隔为1s，希望对初学者有用-this is a counter!0~9999,you can learn this for deep learning~
Deep-understanding-of-FPGA--design
- 深入理解Altera FPGA应用设计-Deep understanding of FPGA Altera application design