搜索资源列表
LED点阵
- 大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。-big screen led to the dot matrix display driver timing. The use of VHDL descr iption language. Rom which documents can be automatically generated using lpm_megcore.
micro uart
- 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
frequency_counter_2(successful)(top-down design).r
- 小巧的频率计数器，VHDL源代码和仿真文件具全，直接从管工程文件拷贝过来。绝对可用。-compact frequency counters, VHDL source code and simulation with all documents directly from the control engineering documents copied. Absolutely available.
USB IPcore（带说明）
- USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
LED七段译码
- 初次上传文件，采用文本格式编辑内容，不知道是否妥当，如有不便之处，敬清各位原谅。-initial upload documents using text format editorial content, I do not know whether they are appropriate, if any inconvenience, King - forgive me.
Visio-绘图21
- 这是asic流程例子.文件内容已经验证过.如有疑问和我联系-This is the process blends example. The contents of the documents has been proven. And I doubt if links
pcm_verilog
- 这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.-PCM telephone transmission system Verilog model of procedures is a modlesim development environment under the project documents, and a waveform simulation results.
usb_funct
- usb1.0的核，有详细的usb核的设计源码，用verilog语言编写，同时附有相关的设计文档，质量不错-usb1.0 nuclear, nuclear usb detailed design source, using Verilog language, along with documents related to the design, quality good
RAM_VHDL
- 该文件时RAM的源文件和测试文件以及仿真文件-the document RAM source document and test papers and documents Simulation
ramrw
- 一个用外部ＭＣＵ通过ＦＰＧＡ来访问外部ＲＡＭ的文件-an external MCU used by FPGA to access external RAM documents
fir_filter
- 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
cordic_beh
- 这是实现cordic算法的一些源程序，各文件的说明可以参见文件内部注释。 -This is the algorithm Coordinate rotation digital source, the documents of the internal documents can be found in the Notes.
color_space_converter
- verlog 编程 色彩空间转换 有测试文档-verlog programming color space conversion is testing documents
ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
timeconstraint
- VHDL编程中的时序约束问题，有两个PDF文件，讲的很详细，需要的立刻下载-VHDL programming timing constraints, there are two PDF documents, said very detailed, immediately download the
cla_vhd
- 超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.-CLA of examples, including source code and test documents, compressed, without a password.
shzizhong
- 文件名称：数字钟设计参考文章 文件信息：4个文件/pdf/－页 语言种类：中文 适合对象：新手/中手 -file names : Digital Clock reference design document article : four documents / pdf /-page variety of languages : Chinese suitable targets : novice / Hand
eqingdaqi
- VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
add_multi
- 移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents
Parall_transfer_seior
- 此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.