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DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码,含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
cotas
- Costas环是用来解调双边带抑制载波信号的,也是二相或四相移相键控信号解调的专用环路-Costas loop is used to double sideband suppressed carrier signal demodulation, and also two-phase or four phase shift keying signal demodulation of the special loop
OK_pll
- 锁相环,带有测试程序,双进双出,可输入任意参数-Phase-locked loop with a test program, double inlet and outlet, you can enter any parameters