搜索资源列表
DupalPortRam.rar
- 基于quartus的双端口RAM的完整设计流程，包括建立的工程仿真实现,Quartus-based dual-port RAM of the integrity of the design process, including the establishment of the Engineering Simulation
actel-fpga-double-port-ram
- 基于Actel FPGA的双端口RAM设计--周立功单片机-Actel FPGA-based dual-port RAM design- ZLG MCU
dual_port_ram
- 实现双口ram的读写功能，并含有测试文件，已经经过方针验证，很好用的-the writing and reading to the dual port ram ,good
jibengongtestbench
- testbench的基本写法，双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of
dpram
- FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
ram
- 一个用VHDL语言编写的双端口存储器程序，可下载在FPGA中使用-Written in VHDL language using a dual-port memory program can be downloaded in the FPGA using
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
RAMtestbench
- 双口Ram的VHDL Testbench-Dual-Port Ram s VHDL Testbench
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
ram_of_Fusion
- Fusion中的双口RAM编写，可以实现双向的调用。用Verilog编写。-Fusion in the preparation of dual-port RAM, you can realize a two-way call. Prepared using Verilog.
ram
- 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
RAM
- 这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充-This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded
dpram2
- vhdl写的双口ram，真正实现双口通信-I write vhdl dual ram, true dual-port communication
dpRam1
- Dual port ram design project developed in Xilinx using VHDL
VHDL
- 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
ram_dp_sr_sw
- dual ram port in verilog
dualportram_asch
- This an asychronous dual port ram-This is an asychronous dual port ram
97288427Dual-RAM
- 双口RAM的具体应用，适合工程开发的入门者(Application of dual port RAM, suitable for beginners of project development)