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ClkScan
- 此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路分为两个子模块，一个提供同步信号（H_SYNC和V_SYNC）及像素位置信息；另一个接收像素位置信息，并输出颜色信号。这样便于进行图形修改，同时也容易实现- This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature
verilog hdl教程135例
- 浅显易懂的vrilogHDL的程序，可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly.
CPLD的跑馬燈
- cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的-cpld entry exchange : CPLD 5,250 cpld an easy-to-use test circuit using VHDL times the
Evita_Verilog
- Verilog 的非常好用易懂的教学软件。-Verilog very handy and easy to teaching software.
Evita_VHDL
- VHDL 的非常好用易懂的教学软件。大家试试看。-VHDL very handy and easy to teaching software. We try.
VLSIrtl_spi
- verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.-Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.
GenericInterruptBlock
- VHDL语言编写的中断模块,是个一般性的设计,可以很容易修改到你自己的设计中去.-VHDL modules prepared by the interruption, is a general design, it is very easy to change your own design.
jop_core_cache
- JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
verilog100
- 有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
fenpin(vhdl)
- 使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
key_prog
- 简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.-easy-to-read 4 * 4 keyboard and display program. To the preparation of other forms of keyboard scan procedures are certain guiding significance.
rtl_DRAM
- 本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.-program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.
mutl16 实现16位移位乘法和除法
- 实现16位移位，可以实现乘法和除法。满足设计要求，实现代码简短，用verilog完成方便，容易操作。-Achieve 16-bit shift, multiplication and division can be achieved. Meet the design requirements to achieve a short code, complete with verilog convenient, easy to operate.
mouse.rar
- 用VHDL编写的鼠标控制程序，经测试运行稳定，且容易修改，升级,VHDL prepared using the mouse control procedures, have been tested to run stable, and easy to modify, upgrade
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
lcd1602.rar
- 通过FPGA做LCD屏的显示控制，简单易学,Done through the FPGA control of LCD display screen, easy to learn
fir.rar
- fir滤波器，Verilog语言写的，容易看懂,fir filter, Verilog language written in easy to understand
VHDL_study
- vhdl实用教程，经典教程，本书特意做了书签，方便初学者查询-vhdl practical course, classic tutorial, the book deliberately made bookmarks, easy for beginners query
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
VHDL-Made-Easy
- Intended for both hardware and sofware designers interested in learning VHDL.HDL (Hardware Descr iption Languages) expertise is a critical, distinguishing skill that is essential to a successful career as an electronics designer. With the booming com