搜索资源列表
PipelineCPU
- 用Verilog实现一个简单的流水线CPU,并运行一个Quicksort程序。这是Berkley,eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
simpleCPUdesign
- 本文档介绍了一个简单的单周期CPU,和流水线CPU的实现过程。 这是我们完成伯克利大学EECS系计算机系统结构课程的实验文档,实验信息见http://www-inst.eecs.berkeley.edu/~cs152/fa05/-This document describes a simple single-cycle CPU, and CPU pipeline implementation process. This is the complete Berkeley EECS Departme
EECS-150---Components-and-Design-Techniques-for-D
- EECS 150 - Components and Design Techniques for Digital Systems