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encoder
- VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。
simple h264 vhdl encoder
- simple h264 encoder，source code and test code in vhdl，简单h264 硬件编码器，源代码及测试，vhdl语言
coder_counter
- 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
oc_mkjpeg
- Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design.
JPEG2000
- jpeg 2000 encoder complete document
chengxu
- 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
Encoder_SSI_Veryilog
- 本文详细描述了SSI协议的通讯格式、原理及应用电路,并采用verilog语言实现了SSI通讯协议.设计实用电路并实现了与绝对值编码器的通讯-SSI protocol described in detail the communication format, principle and application circuit, and use verilog language of the SSI protocol. Practical circuit design and implementat
manchester-decoder-encoder
- Manchester Encoder - Decoder-Manchester Encoder- Decoder
rotary
- Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序-Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light
vhdl
- 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
CRC16bits
- 16bit crc encoder ande demo
s3esk_rotary_encoder_interface
- Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Ro
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
rs_enc
- Verilog code for RS-(255,239) encoder.
verilog
- Verilog jpec coder encoder source code
encoder
- 编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数-the encoder single program
RS
- reed selemon encoder vhdl code
vhdl-JPEG-enc
- JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
Program of 4 to 2 Encoder
- Verilog code for encoder