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Automat
- 设计一个自动售货机控制程序，它的投币口每次可以投入1元、2元、5元，且规定投入1元或2元后不得再投入5元。当投入总值等于或超过设定值（4元），售货机就自动送出货物并找回多余的钱。-design a vending machine control procedures, it can slot into each one yuan, the two yuan, 5 billion there are provisions into one yuan or two yuan may re-enter
ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
trunk-hdlc.rar
- 高级链路层协议的实现，vhdl，fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
fir_sine
- This implementation is moderately memory efficient because it stores only the first Pi/2 radians of sine values. The second Pi/2 radians is a mirror image of the first in time and the second Pi radians is a mirror image in amplitude of the first Pi
four
- 用VHDL语言完成十秒倒计时电路以及四人抢答加分的系统-VHDL language with the completion of 10 seconds countdown circuit and four extra points to answer in the system
NCLPROJECT
- The main objective of the project is to reduce the complexity of the digital circuit with improvement in performance. Two versions of a reconfi gurable logic element are implemented one without extra embedded registration and the other with extr
Mimasuo
- 设计要求(黑体小四，1.5倍行距，段前0.5行) 1）密码预先在内部设置，可以设置任意位密码，这里采用6位十进制数字作为密码； 2）密码输入正确后，密码器将启动开启装置。这里密码器只接受前6位密码输入，并以按键音提示，多余位数的密码输入将不起作用； 3）允许密码输入错误的最大次数为三次, 密码错误次数超过三次则进入死锁状态, 并发出警报 4）报警后，内部人员可以通过按键SETUP使密码器回到初始等待状态； 5）密码器具有外接键盘，可以用来输入密码和操作指令； -Desi
bit_stuffer
- Bit stuffing is used for various purposes, such as for bringing bit streams that do not necessarily have the same or rationally related bit rates up to a common rate, or to fill buffers or frames. The location of the stuffing bits is communicated to
parity_generator
- parity generator Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd num
lock-and-lcd
- 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码
TX
- In data transmission and telecommunication, bit stuffing (also known—uncommonly—as positive justification) is the insertion of noninformation bits into data. Stuffed bits should not be confused with overhead bits. Bit stuffing is used for variou
shouhuoji
- 此机能出售1元、5元、10元。出售哪种商品可由按动相应按键，并同时用数码管显示出此商品的价格； 币的钱数也是有1元、5元、10元三种，但每次只能投入其中的一种币按动相应的一个按键来模拟，并同时用数码管将投币额显示出来； 投币后，按一次确认键，如果投币额不足时则报警，报警时间3秒。如果投币额足够时自动送出货物（送出的货物用相应不同的指示灯显示来模拟），同时多余的钱应找回，找回的钱数用数码管显示出来； 按动确认键3秒后，自动售货机即可自动恢复到初始状态，此时才允许顾客进行下一次购货操作；
berlekamp_parallel
- The Berlekamp multiplier [3] uses two basis representations, the polynomial basis for the multiplier and the dual basis for the multiplicand and the product. Because it is normal practice to input all data in the same basis, this means some basis
vhdl2proc
- vlsi project book. better understanding, good examples. extra solved problems
Extra-Excercise---Moving-Average-Jiten-Bhatt-1130
- VHDL code on implementing a system to calculate moving average
2402-dld
- Multisim® is a schematic capture, simulation, and programmable logic tool used by college and university students in their course of study of electronics and electrical engineering. Multisim is widely regarded as an excellent tool for classroom a
waveform_gen_latest.tar
- 这个核心是一个向前的实现数控振荡器（NCO）-也被称为直接数字频率合成器（DDS）。除了生成标准的正弦/余弦输出波形，它也产生平方和锯齿用很少的额外资源输出。-This core is a straight forward implementation of a Numerically Controlled Oscillator (NCO)- also referred to as a Direct Digital Synthesizer (DDS). In addition to genera