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是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
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该pdf 详细的介绍了 浮点小数的计算法则，和在vhdl程序中 浮点小数的表示方法，和乘除法的运用
希望对大家有用,The pdf in detail the calculation of the decimal floating-point rules, and procedures in vhdl decimal floating-point method, and the use of multiplication and division for all of us hope tha
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介绍一组浮点数的运算代码，包括加减乘除运算的VHDL代码实现-Introduced a set of floating-point code of the operation, including addition and subtraction multiplication and division operations to achieve the VHDL code
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详细介绍双精度浮点数据的格式，以及加减乘除运算的实现方法-Details of the format of double-precision floating-point data, and the realization method of addition and subtraction multiplication and division
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高精度的浮点数除法运算，基于浮点运算的FPGA实现，单精度浮点数-High-precision floating-point division operation, the FPGA based on the realization of floating-point operations, single precision floating point
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double precision floating point algorithm
implemented only division method
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verilog code floating point division
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VHDL语言编写的8位BCD除法器，可以实现浮点数计算，只支持正数运算，并用isim进行仿真-VHDL language 8 BCD division, can achieve floating-point calculations, which only supports a positive number arithmetic, and use isim simulation
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NIOS II中计算浮点数乘除法的函数，可以极大地缩短浮点数运算的执行时间。-Floating-point multiplication and division of functions computed NIOS II, can greatly shorten the execution time of floating point operations.
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使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。-Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.
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VHDL浮点除法运算，VHDL浮点数除法，源码，含仿真图 -VHDL floating point division, source code, including simulation mapVHDL floating point division, source code, including simulation map
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使用vhdl写的32位 64位浮点数加法模块、浮点数乘法模块、浮点数除法模块(Use vhdl write 32-bit 64bit floating-point addition module, floating-point multiplication module, floating-point division module)
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