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DE2_TV
- 这样的设计将DVD视频转换成合适的格式显示在CRT/ LCD显示器。应连接一个DVD视频源,如DVD播放器,在DE2开发板上的VIDEO IN端口。应连接一个CRT/ LCD显示器的VGA端口。应在DVD视频显示在监视器上。-This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should
VerilogHDL
- VerilogHDL程序设计教程,pdf文件格式-VerilogHDL programming tutorial pdf file format
INT_DCT
- Verilog HDL语言实现的整数DCT变换模块。其中包括一维和两维的DCT变换模块各一个。该模块都通过硬件仿真以及FPGA实现后的测试,均满足预期的DCT变换功能。-Integer DCT transfer module with Verilog HDL format. The package includes one 1-D and one 2-D DCT transfer module, which all pass simulation and FPGA evaluation.
vgaV
- vga图像显示电路设计。图像可以自行编辑.mif格式的文件。-vga image display circuit design. The image can be edited. Mif format file.
EDA
- EDA课件中的状态机的学习资料,是PDF格式-The EDA in state machine learning materials, PDF format
prbs
- verilog 格式的prbs数据。可以用于对发射机和接收机的误码率的测试-verilog format prbs data. Can be used for the testing of the transmitter and receiver BER
yibuchuanxingjiekou
- 能进行异步全双工串行通信的模块,该模块以固定的串行数据传送格式收发数据。每帧数据共10 位,其中1 位启动位,8 位数据位,1 位停止位。模块发送的数据由PC 端的串口调试助手接收,要求能发送数字和中文(一首古诗,在FPGA内采用ROM 的方式存储中文内码),并能进行切换。模块接收PC 端串口调试助手发送的16 进制数据,可按10 进制方式显示到LED 上。-Asynchronous full-duplex serial communications module can be performe
RAW2RGB
- 图像由RAW向RGB格式转换的verilog源代码实现-Images from the RAW format to RGB conversion Verilog source code implementation
PWM_IP_TEST
- 自定义PWM的IP核 符合avalon总线格式-Custom PWM IP core is in line with the avalon bus format
VGA
- VGA彩条显示VHDL程序,横竖彩条、棋盘格式-VGA color display VHDL program, anyway color bars, checkerboard format
MATLABLPM_ROM
- 用MATLAB实现LPM_ROM中数据初始化在QuartusⅡ调入ROM初始化数据文件并选择在系统中的读写功能时,默认选择hex文件,在此你是见不到刚刚移动到工程中的mif文件的,需要在右下角的文件格式中选择MIF文件,这样就可以添加进去了-Using MATLAB LPM_ROM initialization data transferred in Quartus Ⅱ ROM initialization data file and select the read and write func
blank
- 监控摄像头传入数据,通过芯片TVP5150转换成数字信号,其中sav_check.vhd检测帧头,converter.vhd将信号转换成Y,Cb,Cr格式,最后write_blank.vhd重新组建完整数字信号,最后通过ADV7171转成模拟信号输出到监视器上。这中间,可以对Y做各种图像处理,如滤波处理,均衡处理,只需要在converter之后添加处理文件即可。-Surveillance camera incoming data through the chip TVP5150 converte
zobrazenie_16_bit_cisla_paralel
- 16 bit switch input view in hexa format on 7seg display
DE2_115_IR
- Verilog IR Receiver decodes and process signal through FPGA and display on the 7-segment displays in hrxadecimal format.
vga_bmp
- 基于VHDL语言读取BMP格式文件,驱动VGA接口在显示屏上显示该图片,并在程序中可控制改图片在显示屏上浮动-Based on the VHDL language to read BMP format files, drives, VGA interface on the screen dynamically displays the picture
blif2vhdl-v1.1
- 将BLIF(Berkeley Logic Interchange Format)格式的电路转换为VHDL代码,使用perl编写,需要perl环境才能使用。 内含BLIF格式的官方说明。-Translate BLIF(Berkeley Logic Interchange Format)circuit to VHDL descr iption, the translator need perl environment to run. Please check you have related t
cordic_0_2pi
- 这个是CORDIC算法 是16位的 Q14格式,运算范围为0~2pi,已经在quartus得到验证。-This is the CORDIC algorithm is a 16-bit Q14 format operation range is 0 ~ 2pi, has been verified in quartus.
hdmi_20130227
- (1)包含驱动HDMI编码芯片Sil9134的时序逻辑和寄存器初始化代码,输出测试图像格式为1080P@30Hz;(2)使用Vivado2013.3开发,硬件平台为威视锐Zing开发板,搭载Xilinx Zynq7020芯片。-(1) contains drivers HDMI encoder chip Sil9134 timing logic and register initialization code, output test image format 1080P @ 30Hz (2)
kaoshi
- FPGA -计数器,29减法计数器。使用verilog hdl编写格式,cyclone I 系列EP1C3TC144芯片。-FPGA programming using 29 down counter, using verilog hdl written format, cyclone I series EP1C3TC144 chips.
mouse_led
- mouse to led movements to realize where the x and y coordinates. After the first falling-edge tick and the rx-en signal are asserted, the FSMD shifts in the start bit and moves to the dps state. Since the received data is in fixed format, we shift