搜索资源列表
frame_ctrl
- 控制帧格式，实现组帧的的各个功能，程序比较长-Control frame format to achieve the various functions of the frame group, the program longer
CRC_Check
- crc校验的vhdl验证，模块分为编码组帧解帧解码模块-vhdl crc checksum verification, the module is divided into coding frame decoding module framing solution
syn_search
- 设计一检测电路，搜索帧同步码。要求在搜捕态能够正确地从数据流中提取帧同步码，在达到一定设计要求时进入稳定同步态。同时，要求帧同步检测电路具有一定的抗干扰能力，在稳定同步态发现帧失步次数超过设计要求时，系统要进入搜捕状态。-Design a detection circuit, the search frame synchronization code. Required to search state can correctly be extracted from the data stream
ethernetframe
- 实现ethernet帧的解析，读入一个文件，将文件中的帧逐个解析并输出，进行CRC校验-Ethernet frame to achieve the resolution, read a file, the file-by-frame analysis and output, the CRC check
M-sequence
- M序列具有伪随机特性，代码包含了M序列的生成和检测，可用于帧同步系统。-M-sequence has a pseudo-random properties, including the M-sequence code generation and detection, can be used for frame synchronization system.
check_net_test
- 用来检查FPGA通过PHY发送数据时是否有掉帧的现象-FPGA is used to check whether the PHY sends the data out of the frame with the phenomenon of
sd
- 一个基于verilog的数码相框的实现,全是verilog写的,里面包括一个sd驱动的文件系统-Verilog-based implementation of digital photo frame, all written in verilog, which includes a file system driver sd
synchronization-clock-generation
- 引入了D 触发器的长帧同步时钟的产生,其是一个时钟分频的例子，特别提醒了如何在程序中引入触发器，适合初学者引用。-The introduction of the D flip-flop of long frame synchronization clock generation, it is an example of a clock divider, remind how the introduction of the program Trigger reference for begin
VHDL-zhengtongbutiqu
- 基于VHDL帧同步提取建模与设计 该设计主要是在一帧数据的前后插入巴克码-Based on VHDL frame synchronization extraction modeling and design
data_syn_check_47
- 帧同步搜索,用控制数据替换MPEG-2 TS流中的空帧-Frame synchronous search,Replace MPEG-2 TS stream by using the control data
DE2_LCM_CCD_detect_b
- 本程序基于Altera公司的DE2平台完成仓库的实时监控并对移动的目标进行自动识别和报警的FPGA设计，研究重点就是图像采集和移动目标识别的FPGA实现。采用Altera公司的DC2模版对视频进行采集并将采集到的图像信息进行缓存，通过监视器实时显示，采用帧间差分法对采集到的帧图像进行运动检测，当仓库中有运动情况的时候，两个图像间灰度会出现异常，通过对灰度异常的侦测完成仓库移动目标的识别并蜂鸣器报警。-Complete real-time monitoring of the warehouse a
XILINX-PCI-E-DRIVER
- Xilinx公司的FPGA基于V5的开发版PCI-E驱动程序，可用作图像采集卡以及数据处理用-Xilinx s FPGA-based V5 Developer Edition PCI-E drivers can be used as a frame grabber, and data processing
DE2_70_TV_sobel.7
- DE2_70_TV與DE2_70_D5M_LTM的架構非常類似，都是以SDRAM當做frame buffer，所以若要加上演算法，基本上也是放在SDRAM之前做前處理，或者放在SDRAM之後做後處理。-The architecture DE2_70_TV and DE2_70_D5M_LTM very similar, as a frame buffer, so coupled with the algorithm to, basically on the SDRAM before doing
frame_cap
- GPON中下行帧捕捉模块的verilog程序，在quartuaII上已经验证过，需要的可以拿去参考下-GPON downstream frame capture verilog program has already been verified in quartua can take to refer to the following
zhentongbu_VerilogHDL
- 帧同步的VHDL程序源代码，巴克码同步实现。-Frame synchronization of the VHDL source code, Barker code synchronization
syn_detc
- Verilog语言的同步帧检测模块，适用于pcm通信系统，本模块可检测的同步帧为100110-The synchronization frame detection module implemented use Verilog language,for pcm communication system, the module can detect synchronization frame for 10,011,011
Verilog-HDL-digital-system-design
- Verilog HDL数字系统设计教程,其中对Verilog HDL语言的语法，FPGA的结构及其应用作了详细的讲解-Verilog HDL digital system design introduces the Verilog HDL language and the FPGA function including syntax ,FPGA frame and application and so on
h.264
- 包含h.264的包括帧内、帧间、变换编码、熵编码的vhdl源程序-Contains the vhdl source h.264 frame, frame, transform coding, entropy coding
led_RS232
- 串口通信实例，单片机发送一帧数据，上位机接收，并点阵显示，模拟16*16LED点阵效果。-Examples of serial communication, microcontroller sends a frame data, the host computer receives, and dot matrix display, analog 16*16LED lattice effect.
NIOS_uip_snapshot_sd
- 這個程式主要是實作，可經由browser發出請求從de2上取回影像(bmp/jpg)，取回影像同時會將該影像寫入sd卡 構架部分先將輸入影像取1/16至320x256，因為cpu不是很夠力，先在比較小的圖上做-This program is implemented, via the browser makes a request to retrieve images from de2 (bmp/ jpg), to retrieve images sd card at