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DaFilter
- /* This program generates the DApkg.vhd file that is used to define * the DA filter core and gives its parameters and the contents of the * Distributed Arithmetic Look-up-table \"DALUT\" according to the DA algorithm-/ * This program generate
caisezhuanhuan
- 现色彩空间转换R’G’B’ to Y’CbCr的VHDL源代码。
xapp283
- YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
RGBtoYCbCr
- 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
hilbert_transformer_latest.tar
- The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hil
23-10111
- a simple serial to parallel converter using XILLINX and VHDL (the number of the project represents the binary code used by the converter e.g 23- 10111)
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
FSM_3
- Final state machine written on VHDL in Quartus II. Imple. Implements the working principle of a sensor which detect the spinning direction (e.g. a motor) and depending on the direction a DuplexCounter is set to "up" or "down" mode.
YUV2RGB
- 该代码可将YUV图像数据转换为VGA显示器能显示的RGB数据，R,G,B的位宽均为4，转换速度快。-The code can be converted to a YUV image data of RGB VGA monitor can display the data, R, G, B of the bit width of 4, the conversion speed.
jishuqi
- 一个9999的计数器，然后用4个数码管显示当前数值，数码管共用a到g口，通过com1到com4选通的- 9999 counters, then with 4 nixietube demonstration current value, the nixietube use in common a to g, through com1 to the com4 selection
CIEDE2000
- CIEDE2000计算实例，每个步骤都有，计算最新的色差公式-Ref: G. Sharma, W. Wu, E.N. Dalal,"THE CIEDE2000 COLOUR-DIFFERENCE FORMULA: Implementation Notes, Supplementary Test Data, and Mathematical Observations," submitted to COLOR RESEARCH AND APPLICATION, Jan 2004.
CPU
- 用Verilog HDL语言写一个简单的处理器CPU。包括IR,Control unit,A,Addsub,G,Counter,8个寄存器。-Verilog HDL language used to write a simple processor CPU. Including IR, Control unit, A, Addsub, G, Counter, 8 registers.
jiaotongdeng
- A方向为主干道，B方向为支干道。分设红（R）、黄(Y)、绿(G)和左拐(L)四盏灯。1表示灯亮，0表示灯灭。四灯的点亮顺序为：绿灯→黄灯→左拐灯→黄灯→红灯，A方向四个时间为55秒（红）、40秒（绿）、5（黄）秒和15（左拐灯）秒；B方向的四个时间为65秒（红）、30秒（绿）、5秒（黄）和15（左拐灯）秒。时间要改变只要改变计数器的预知数即可。-A direction for the main road, B direction of branch roads. Divided red (R),
32p-Soc-G.3DS-Proteus-ARES
- 3D Model to Proteus/ARES 3D PCB Visualization
fifo
- 是在quartus ＩＩ软件的中编写的ｆｉｆｏ模块的ｖｅｒｉｌｏｇ ＨＤＬ硬件描述语言代码，提供给大家希望对大家有一定的而帮助。-fjwe fe w w4 twtw43t4 t3fsjs fsd f swefw gewr ge ger g e t 3ewutowj otweu to teow t3o tewr to t3t t3e rtweo t3w 34 t34 o3tjwkl sj ter k.
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
digitron_driver_VHD
- 关于easy fpga开发板的led数码管的驱动； --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个
digitron_driver_V
- 关于easy fpga开发板的led数码管的驱动； 此为verilog程序 --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时
hdbn_latest.tar
- This “core” is actually two cores – an HDB3/HDB2/B3ZS Encoder that converts NRZ data into P and N pulses according to ITU-T G.703, and a HDB3/HDB2/B3ZS Decoder that converts P and N pulses into NRZ data according to ITU-T G.703.
qi-duan-yi-ma-qi
- 七段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用译码程序在FPGA\CPLD中来实现。本实验作为7段译码器，输出信号LED7S的7位分别是g、f、e、d、c、b、a，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别为1、1、0、1、1、1、0、1。接有高电平段发亮，于