搜索资源列表
HDLC
- verilog HDL语言编写的HDLC协议的IP核，包括通讯控制及CRC。-written in verilog HDL HDLC protocol IP core, including communications control and CRC.
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
HDVideoEncod
- HD Video Encoding with DSP and FPGA Partitioning White Paper
altera_mf
- 高清或标清SDI信号，通过编写的FPGA的Audio程序进行处理。-HD or SD SDI signals, through the development of the FPGA-Audio procedures.
sd_hd_sdi_demo
- lattice的SDI DEMO板工程源代码，HD/SD自适应，内有彩条自产生源-designed for lattice sdi
audio_bargraph
- Allows to display an audio bargraph (peak meter and vu meter) of a HD-SD SDI embedded audio signal .
taxivhdl
- 出租车计价器VHDL程序与仿真。--文件名：taxi.hd。 --功能：出租车计价器。 -Taximeter VHDL procedures and simulation.- File Name: taxi.hd.- Function: taxi meter.
VHDL
- 实用教程[完整版]_潘松_PDF高清我看了一下 感觉还行-Practical Guide [Full] _ Pansong _PDF HD feel good I looked
HD-NIOS
- 基于NIOS的高清系统设计，文章的名字是基于NIOS的高分辨率图像采集系统设计-NIOS-based HD system design, the article' s name is based on the NIOS high-resolution image acquisition system
EVMDM6467HD1080P_CPLD
- TI的TMS320DM6467 HD 1080P 开发板CPLD源码-TI' s DM6467 development board CPLD source
HD
- 這是半加器的代碼，希望對大家有些用，不足之處請見諒-This is a half adder code, we want to use some, please forgive the inadequacies
HD_top_null
- It s HD quad code . VHDL for Altera s cyclone4
GV8500_Data_Sheet
- HD-SDI线驱芯片的资料，讲述SDI工作原理，对SDI初学都很有帮助！-HD-SDI cable driver chip information about SDI working principle of SDI are very helpful for beginners!
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111
vmodcam-ref-hd-demo-12
- 通过fpga控制从vmodcam中获取视频数据并通过vhdmi发送到显示屏上-And sent via fpga control access to video data from vmodcam on display through vhdmi
vmodcam-ref-hd-demo-13
- 通过fpga控制从vmodcam中获取视频数据并通过vga发送到显示屏上2-Fpga control access to video data from vmodcam and send to the display via vga 2
init_LCD
- Initializes Toppoly TD043MTEA1 LCD. R02: Type 1 Dot inversion, VD and HD low polarity, Latch data on falling edge, 800x480RGB R03: Software register standby, pre-charge enabled, 100 drive capacity, PWM enabled, VGL pump enabled, cp_clk enabled, n
Ex26_RS232
- 串口RS232实现，使用Verilog hd语言-rs232,verilog hdl
sdi_3g_hd_sd_code
- SDI格式视频产生代码，fpga编码，里面有3个文件分别对应3g,hd,sd信号，给不同的时钟就可以直接用了-SDI format video generation code