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DCT_vhdl
- IDCT-M is a medium speed 1D IDCT core -- it can accept a continous stream of 12-bit input words at a rate of -- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video -- the core is 100％ synthesizable-IDCT-M is a medium speed
erweiDCT
- 一种改进的一维DCT方案设计与实现,采用VHDL实现,DCT以及IDCT
8x8IDCT
- 8x8 iDCT verilog code 一次輸入八個點
IDCT
- 用verilog HDL语言编写的IDCT程序，可以计算8*8的整形数矩阵，用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
attachments_2010_01_29
- dct and idct vhdl code
DCT_IDCT
- verilog code for DCT and IDCT (JPEG)
DCT_IDCT
- H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码-H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code
dctidct
- dct and idct code for verilog
Axi_mux
- The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the lib
idct
- invert discret cosinus transformation VHDL code
IDCT
- HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architect
DCT_IDCT
- DCT and Idct with vhdl and verilog