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  1. qdq_new

    0下载:
  2. 采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理,整个电路可划分为三部分:采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divi
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:64.03kb
    • 提供者:huhu
  1. zlqdq

    0下载:
  2. vhdl编写的智力抢答器程序,比较简单,仅供参考-vhdl prepared by the intelligence Responder procedure is relatively simple, for information purposes only
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:2.69kb
    • 提供者:george
  1. AltiumDesigner6

    0下载:
  2. Altium Designer 6 Training for FPGA,Software andSystemsDevelopmentEmbedded Intelligence Training
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:5.9mb
    • 提供者:颜奇麟
  1. 1137198913

    0下载:
  2. altium designer 6 Training for FPGA,Software andSystemsDevelopmentEmbedded Intelligence Training
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:16.64kb
    • 提供者:jrhong
  1. qiangda

    1下载:
  2. EDA课程设计智力抢答器 四路抢答器的设计以及程序和视屏 软件运行环境是:Quartus 9.1-EDA curriculum design intelligence Responder four answering device design and process and Screen software operating environment is:Quartus 9.1
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-26
    • 文件大小:8.74mb
    • 提供者:shaozhen
  1. 1MEMOCODE4_dave_contest

    0下载:
  2. Hardware Acceleration of Matrix Multiplication a Xilinx FPGA Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan Computer Science and Artificial Intelligence Lab Massachusetts Institute of Technology Cambridge
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:120.77kb
    • 提供者:lance
  1. Intelligence-contest-for-vies

    0下载:
  2. 智能竞赛抢答器的FPGA实现,包括设计要求,设计思路,设计源代码,设计仿真结果。-Responder Smart contest the FPGA implementation, including design requirements, design ideas, design source code, design and simulation results.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2015-04-27
    • 文件大小:192kb
    • 提供者:csh
  1. jifenqi

    0下载:
  2. 基于vhdl的智力抢答器的程序设计,功能包括抢答 积分 减分 亮灯 等-Responder based on intelligence vhdl program design features include the answer in points by sub-light, etc.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-03
    • 文件大小:42.13kb
    • 提供者:tulufan
  1. 3_first_event_detector

    0下载:
  2. 本代码实现智力抢答器的功能,采用VHDL语言。全部实现过程全在文件里面,结构清晰,思想明了。-This code realization of intelligence responder function, using VHDL language. The whole implementation process full in files, clear structure, clear thinking.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-02
    • 文件大小:553.63kb
    • 提供者:张天健
  1. yui_v68

    0下载:
  2. MIT Artificial Intelligence Laboratory identification of the target source, Bayesian parameter estimation principle mixed logit model, Various resource allocation algorithm.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-27
    • 文件大小:5kb
    • 提供者:yiuniuqui
  1. vctqf

    0下载:
  2. Course designed to prepare the matlab program code, MIT Artificial Intelligence Laboratory identification of the target source, Nonlinear discrete system identification.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-28
    • 文件大小:7kb
    • 提供者:tyasiu
  1. fen_v67

    0下载:
  2. MIT Artificial Intelligence Laboratory identification of the target source, There CDF trigonometric curve / 3D graphs, Can realize the two-dimensional data clustering.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-26
    • 文件大小:7kb
    • 提供者:sansiehuigeng
  1. tpjpr

    0下载:
  2. Use matlab intelligent predictive control algorithm, MIT Artificial Intelligence Laboratory identification of the target source, Undergraduate complete set requirements refer to the standard test models.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-24
    • 文件大小:6kb
    • 提供者:gingkouhen
  1. tj371

    0下载:
  2. MIT Artificial Intelligence Laboratory identification of the target source, Automatic identification in the matlab environment the size of the connected area, Target can be extracted in a picture you want.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-30
    • 文件大小:8kb
    • 提供者:kmutqekj
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