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FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
mnxhjc
- 本实验用DA转换＋比较器的方法对外界模拟信号进行检测，同时这种联合装置加上CPLD可以代替低频AD转换器的功能。-this experiment + DA conversion method of comparison to the outside world analog signal detection, while such joint CPLD devices can be replaced with low-frequency AD converter functions.
ug_memrom.rar
- quartus 与 MATLAB 联合仿真，生成rom表，,Quartus joint simulation with MATLAB to generate rom table,
Quartus_fft_ip_core.rar
- Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试),Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
jpeg
- JPEG(Joint Photographic Expert Group,联合摄影专家组)编码的数据执行解压缩的各项功能.JPEG的VHDL实现代码-JPEG (Joint Photographic Expert Group, Joint Photographic Experts Group) encoding of data to implement the various functions of decompression. JPEG realization of VHDL code
Modelsim
- modelsim 的使用具体方法与步骤 以及与Quartus联合仿真-ModelSim the use of specific methods and procedures, as well as a joint simulation with the Quartus
DEMO3_KX8051_GPS_FTEST_2C5
- 此示例是8051核加频率计的联合设计,带有8051IP核资料-This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP
IterativeDecodingofBinary
- In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
AD_DA
- 用VHDL语言编写的ＡＤＤＡ控制接口程序，联合调试的。-VHDL language with the ADDA control interface program, the joint debugging.
P_157
- From Joint stereo to spatial audio coding
matlab_quartus
- 用于matlab和quartus的联合开发-For the joint development of matlab and quartus
2007_Xilinx
- 2007年Xilinx 联合实验室主任会议 FPGA设计时序收敛-2007 meeting of directors of Xilinx FPGA Design Joint Lab timing closure
ED-Aand-Verilog_HDL
- EDA和verilog联合使用，是FPGA开发的利器-EDA and the joint use of verilog is FPGA development tool
MI
- PS2的键盘解码和led灯显示解码的联合，适合初学者，VHDL程序-PS2 keyboard decoding and joint decoding led light display, suitable for beginners, VHDL program
DE2_SD_Card_Audio
- 基于EP2C35F672Ｃ的ＥＤ２实验板自带源文件。DE2_SD_Card_Audio，ＳＤ卡和音频系统的联合操作。-ED2 based on the experimental board comes EP2C35F672C source file. DE2_SD_Card_Audio, SD card, audio system and the joint operation.
1602lcddisplay
- 1602液晶显示程序 用51单片机与cpld联合控制 作为参考-1602 LCD program with 51 SCM and CPLD joint control as reference
FM_DemodNew
- FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真-FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation
CPU_Sinple
- 实现单周期CPU，完全按照设计图设计出各个部件后用函数联合成CPU。-Function joint completely designed in accordance with the design of the various components to achieve single-cycle CPU to CPU.
Digital-stopwatch
- 数字秒表，用VHDL语言描述，用层次设计概念，将设计任务分成七个子模块，规定每一模块的功能和各模块之间的接口，然后再将各模块合起来形成顶层文件联试。-Digital stopwatch, using VHDL descr iption, level design concept, the design task is divided into seven sub-module to provide the interface between each module functions and m
fpga_ctl
- niosII和VHDL的联合应用，VHDL编写基本框架，C++编写niosII应用程序-joint application niosII and VHDL, VHDL prepared a basic framework, C++ to write niosII application