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lab6
- this verilog file gives the user an ability to program the switches on an altera board
Lab6
- 采用ISE10.1，VHDL语言数字时钟的设计，压缩包为源程序代码-By ISE10.1, VHDL language digital clock design, source code for the compressed
Lab6(result)
- VHDL的小程序，可实现4bits输入的循环-VHDL small procedures, can enter the cycle 4bits
lab6
- verilog code for clock
lab6
- vhdl seven segment displayer
Computer-Architecture-lab6
- 计算机组成实验作业6，fpga开发板，verilog语言编写-Composition of experimental computer operating 6, fpga development board, verilog language
lab6
- 有关加法器的操作处理，内涵简单加法器一直到八位带进位加法器编程，附有word文档描述-Related to the handling of the operation of the adder, the connotation of a simple adder to the eight into the adder programming attached word document describes
lab6
- 在赛灵思的Spartan-3E开发板上做的跑马灯项目，用switch开关控制跑马灯类型-Marquee project in Xilinx Spartan-3E development board to do the switch switch control Marquee type
lab6
- ISE 13.4中SDK开发时的时钟中断程序，实现每秒产生中断，并由led灯显示-The ISE 13.4 SDK development clock interrupt program, the interrupts generated per second, by led lights display
lab6
- de2 altera 实验7 finite state machines 答案-de2 altera experiment 7 finite state machines answer
lab6
- 详细描述设计过程和实验中遇到的问题，包括： ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） 实验总结，在调试和下载过程中遇到的问题
lab6-3-8DECODER
- 数字设计和计算机体系结构：用verilog语言描述3-8译码器的设计与实现-Digital design and computer architecture: use verilog language describe 3-8 decoder design and implementation
lab6
- 使用vivado和Xilinx开发板实现VGA图像显示，开发板为Xilinx Artix-7(Using vivado and Xilinx development board to realize VGA image display, the development board is Xilinx artix-7)