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Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码,它的直接编码运算量较大,通常具有码长的二次方复杂度.为此,利用有效的校验矩阵,来降低编码的复杂度,同时研究利用大规模集成电路实现LDPC码的编码.在ISE 8.2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程,为LDPC码的硬件实现和实际应用提供了依据-Abstract:Low.density parity·check code(LDPC code)is a kind of linear eror
SPA
- 首先介绍了LDPC码的校验矩阵和其因子表示方法,然后利用二分图对和积解码算法进行了详细的描述,最后给出了信度传播概率译码算法详细步骤,并对关键公式作了证明-This paper,first introduces the check matrix and the factor graph of LDPC,then describes the sum-product algorithm by using the factor graph,and finally presents the deta
Inter_Rom
- 交织器(用LDPC译码,H矩阵交织器书写方法)希望有用-Interleaver (with LDPC decoding, H matrix interleaver write methods) seek to help
LDPC-long40rate0.5-encode-and-decode
- LDPC的短码,码长为40速率为0.5的LDPC码的设计,用的是QC矩阵,压缩文件为原码部分,工程太大传不上去。-LDPC short code, a code length of 40 rate of 0.5 LDPC code design, using a QC matrix, the compressed file is part of the original code, do not pass up the works too.
ldpc-code
- ldpc codes are low dencity paRity checking matrix to check the parity on matrix based g and h algorithm based on algorithm matrix input will be added to this code