搜索资源列表
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
m15
- 扩频通信M序列,编码,通用VHDL语言-M sequence spread spectrum communication, coding, generic VHDL
pseudorandom
- 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
3
- 基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列
mcode
- 用VHDL语言生成m序列，进行扩频。m序列是10级的。-m sequence
m.rar
- 扩频接收机设计的部分，一个用vhdl语言编写的m序列生成器，,A language with vhdl generator sequence m
m_vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）-m sequence vhdl
m
- vhdl,序列信号发生器，发出11101010，可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
2mxulie
- 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m
VHDlsheji
- 本文介绍了一种使用VHDL 设计多波形m 序列 发生器的原理与实现方法。-This paper presents a VHDL design using multi-waveform m sequence generator principle and realization method.
mvhdl
- 此文件中包含m序列发生器详细的vhdl源码，欢迎各位下载-it is a file of m porducor based on vhdl
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
vhdl--eda
- m 序列发生器 计数器 七段数码管显示 bcd 十六进制转换-failed to translate
PSK-modulator-design-using-VHDL
- 用VHDL语言编程来实现PSK调制器的设计，1）产生基带序列 ，此处用M序列 2）完成PSK调制 -PSK modulator using VHDL language programming to design, 1) generates the baseband sequence, here M-sequence 2) complete the PSK modulation
m
- 这是vhdl编写的产生7位m序列的程序，类比可以产生更多为的。而m序列即可作为输入测试信号，也可以模拟噪声。-It is written vhdl 7 m sequence generation process, can produce more for the analogy. The m-sequence can be used as an input test signal, it can simulate noise.
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
fpga代码
- 实现了m序列产生，同步信号提取功能，实现了所有功能(The m sequence is generated and the synchronous signal extraction function is realized)