搜索资源列表
state-machine
- 状态机，独热码实验，简单的Verilog语言设计For NJU，简单易行-State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
state-machine-design
- 状态机设计的苦干个不错的例子，ＶＨＤＬ语言编写，相信会对verilog的学习者有帮助-State machine design a good example of hard work, VHDL language.Ｉthink it will help verilog learners
howwite_status_machine_with_Verilog
- 如何用verilog语言写好状态机的不错的文档，希望对大家有所帮助-How to use Verilog state machine language to write good documentation, I hope all of you to help
softdrink
- 自动售货机实现，采用VERILOG语言编写源码，与大家分享，共大家参考-Vending machine implementation, the use of language VERILOG source to share with you a total of U.S. reference
source_code
- 一个用c语言编写的自动售货机控制器源代码-A with c language source code for vending machine controller
Automachine_project
- verilog 语言写的自动售货机程序，系IC课程设计代码，QUARTUS -verilog language written in a vending machine program, the Department of IC curriculum design code, QUARTUS II
statemachine
- 一个用vhdl语言写的交通灯控制的例子，可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use.
cop2000
- 模型机仿真的VHDL语言描述，在xilink9.1环境中实现。-VHDL simulation model of machine language to describe, in xilink9.1 environment implementation.
auto
- verlog语言编写的自动售货机源代码，可供初学者参考 -verlog vending machine language source code reference for beginners
verilog
- 用verilog语言进行状态机的时序与功能仿真-Verilog state machine language with timing and functional simulation
state-machine-code
- 用Altera Quartus II 的VHDL语言完成的状态机控制步进电机的程序员代码-The use of Altera Quartus II VHDL language to complete the state machine code programmer stepper motor control
state-machine-
- VHDL语言状态机的源程序，有助于学习VHDL语言的状态机-VHDL state machine of the source language to help learn the language of the state machine VHDL
Verilog-state-machine
- 状态机采用 VerilogHDL 语言编码，建议分为三个 always 段，本文档就是详述其原因-VerilogHDL language code using the state machine, the proposed section is divided into three always
State-machine
- 实现了一个简单状态机的转换功能，用Verilog语言。-State machine implements a simple conversion function, with the Verilog language.
washing-machine
- 用VHDL语言实现洗衣机的模拟功能，内容完整，对学习很有帮助-Washing machine in VHDL language simulation, content integrity, and for very helpful
mealy_sequence
- 实现米粒状态机 用verilog语言实现状态机的过程-Implement a state machine with a grain of rice verilog state machine language course
Air-conditioning-state-machine
- VHDL语言编的一个空调控制系统。cpld实验中的代码-VHDL language a series of air-conditioning control system. the cpld experiments code
verilog-state-machine
- 使用VerilogHDL语言的小教程。 用三段式方法编写状态机。 有清晰详细的注释。-A small tutorial teaching how to write the state machine using three-step method in VerilogHDL language. There are clear and detailed notes in the tutorial.
Enumeration-type-state-machine
- 使用列举类型的状态机VHDL语言编写，亲自运行，无错-Enumerated state machine VHDL language, personally run error-free
step-machine
- fpga课程设计中的步进电机简易编程代码，VHDL语言。-FPGA curriculum design stepper motor simple programming code, VHDL language.