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VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块,各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
Getting-Started-with-HW
- 采用zedboard、zynq等在matlab的平台上进行硬件协仿真的,文章介绍Getting Started with HW,环境的搭建和调试方式。-Using zedboard, zynq etc. on matlab platform for hardware co-simulation, the article describes the Getting Started with HW, build and debug mode environment.