搜索资源列表
firmatlab
- fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
fftmatlab
- fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
ddsmatlab
- dds在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-dds dspbuilder under the VHDL source code and test incentives document matl ab model, the simulation under through modelsim
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
sinmdlmatlab
- 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
DDS_SINWAVE
- matlab下，用dspbuilder实现dds模块产生正弦波的源码，-Matlab and used to achieve dds dspbuilder produce sine module source code,
PSKmoudel
- matlab下，使用dspbuilder实现的psk调制模块的源码-Matlab, the use of dspbuilder realized psk modulation source module
ASKmoudel
- matlab下，使用dspbuilder实现的ask调制模块的源码-Matlab, the use of dspbuilder realized ask modulation source module
dds正弦发生器代码
- 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for sim
verilog
- verilog语言例题集锦 包含加法器，乘法器，串并转换器等verilog源代码-Example Collection contains verilog language adder, multiplier, and converters, such as string verilog source code
c2812rtdxtest_c2000_rtw
- 由MATLAB生成的RTDX的源代码，由模型搭建，然后自动生成DSP的源代码-RTDX generated by MATLAB source code, set up by the model, and then automatically generate DSP source code
digital_filter
- 数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
DDSsinwave
- matlab下，用dspbuilder实现dds模块产生正弦波的源码-matlab under dds with the realization of dspbuilder generated sine wave source modules
Visio-schemat_blokowy_niezawodno____
- ps2 keyboard verilog source code, to support the ascii code. scan code output, the expansion of key output, press and release the information output
FPGA_Book_cd
- 《无线通信FPGA设计》包含的所有例子源码，包括matlab仿真和verilog源码，本书内容还是非常丰富的，涉及无线通信领域各个方面。不过对于一些比较新的技术，其FPGA实现部分过于简略，难以在工程中实用化。-" Wireless FPGA Design" contains all the examples source code, including the matlab simulation and verilog source code, the contents of
daima
- 关于《无线通信FPGA设计》的源代码，有matlab和fpga的实现，非常好，特别是对于做信号处理的。-On " Wireless Communications FPGA design" of the source code, there is matlab and fpga implementation, very good, especially for doing signal processing.
fir_PGA
- 一种基于verilog的fir滤波源码，并带matlab仿真源程序。-Based on the fir filter verilog source code and source code with matlab simulation.
lagrange
- matlab源代码很有用那个的软件，配合许多电子软件使用-matlab source code
8bitcpunew
- 设计一个8位的CPU 有完整的程序包 仿真结果-Modern communication system ( MATLAB ) Edition ( Second Edition ) MATLAB+ source code for all
MATLABPQPSK_final
- QPSK调制解调，载波同步的matlab源程序，测试通过无bug-QPSK modulation and demodulation, carrier synchronization matlab source code, test bug-