搜索资源列表
MIPS32ALU
- VHDL MIPS 32位ALU的设计，基于Quaryus II平台-VHDL MIPS 32 位 ALU design platform based on Quaryus II
alu_arm_alu_mips
- 加法器的arm实现和mips实现，alu_arm,alu_mips,南大计算机系计算机组成原理实验-Adder arm to achieve and realize mips, of alu_arm alu_mips, Nanda, Department of Computer Science Computer principle experiment
MIPS_CPU
- 一个完整的MIPS CPU的设计，是创新设计项目，内含详细的项目设计报告-A complete MIPS CPU design, innovative design projects, detailed project design report containing
MIPS32Barrelshifter
- VHDL MIPS 32位桶形移位器的设计-VHDL MIPS 32-bit barrel shifter design
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
DES_IP
- 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
mipsfinal
- 用vhdl设计的一个mips小型cpu，不带流水，有r类，i类，j类指令都有~·-Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
MIPS_IP
- 经典的RISC 计算死体系MIPS 源码VHDL版-Classic RISC MIPS source computing system for VHDL version of death
finished369phase1
- phase 1 of mips computer architecture
MIPS_CPU
- MIPS结构的CPU，采用VHDL编码，附带验证程序，能够跑题hash算法，流水灯，求π程序-MIPS structure of the CPU, using VHDL coding, with the verification process, to get off track and hash algorithms, water lights, find π procedures
ALUC
- 用verilog语言中xilinx平台上实现single ALU,包括alu的基本MIPS指令运算,ALU control的实现-Xilinx verilog languages with the platform to achieve single ALU, including the basic MIPS instructions alu operations, ALU control implementation
prelim
- Mips implementation core in vhdl
MIPS_UNI_v0
- verilog mips unicycle
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
Pipelined_CPU
- 此程序是关于MIPS的RSIC架构的带有流水线功能的源码，对于RSIC_CPU的初学者在理解RSIC系统上有很大的帮助。-This program is about the RSIC architecture MIPS pipelined function with source code, for novices to understand the RSIC RSIC_CPU system is very helpful.
pyball
- Hex type memory file. Used to update memory in a simple MIPS processor
CPU
- 基于32位MIPS流水线CPU，由自己独立完成，-Pipelined 32-bit MIPS-based CPU, by themselves independently,