搜索资源列表
mips
- cpu---risc---mips源代码-cpu---risc---mips
CPU
- 基于32位MIPS流水线CPU，由自己独立完成，-Pipelined 32-bit MIPS-based CPU, by themselves independently,
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
CPU
- mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
mips_core
- mips的一个模型,基本实现了mips处理器功能-a model for mips cpu。
mips_cpu_final
- 一个8位的mips cpu，采用VHDL语言编程。-this is a 8 bits mips cpu core which is writed by vhdl
project3
- mips single cycle cpu
MIPS_cpu_verilog
- 带流水线的类MIPS CPU verilog源代码-With lines of class MIPS CPU verilog source code
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
MIPS
- 用verilog语言描述的CPU各部分及相关链接-It about CPU s component and relationship which use verilog
pipeline_code
- 实现了MIPS五级流水CPU,用verilog语言实现-MIPS CPU verilog
vhdl-pipeline-mips0
- MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
minimips_latest.tar
- minimips MIPS CPU源码，包括文档说明-minimips CPU source code documentation etc
Lab7
- CSCE2214课程设计，试验7源代码。实现单周期的MIPS CPU 16位。-CSCE2214 curriculum design, test 7 source code. Achieve single-cycle MIPS CPU 16 place.
Lab9-Forwarding-Unit
- CSCE2214课程设计，试验9源代码。实现流水线结构的MIPS CPU 16位。配有强大的Forwarding Unit.-CSCE2214 curriculum design, test 9 source code. Implement pipelined MIPS CPU 16 place. With a strong Forwarding Unit.
single-CPU
- 单时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Single CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
simple-pipeLine-CPU
- 简单的流水线CPU实现，基于MIPS指令集。-Simple pipelined CPU implementation, based on the MIPS instruction set.
cpu
- 用vhdl实现了具有流水的cpu，实现30条基于mips指令的指令集-Achieved with vhdl cpu with water, to achieve 30 mips instruction based instruction set
多周期cpu
- 多周期cpu,11条mips指令集，仅供参考