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auk_rtprx-v3.1.0.tar
- The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction
SATA-Connectivity-solutions-for-Xilinx-FPGAs.pdf.
- This gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for b
FPGA
- FPGA交通灯说明： 1. 本程序使用VHDL加原理图方式设计而成。 2. 实验时，使用Quartus II软件完成了工程管理与下载验证，使用max+plus II软件进行了功能仿真。 3. 由于实验当时对原理图文件缺乏足够的认识，导致原原理图以及仿真输出文件已经丢失。现在的工程 RTL视图以及仿真输出波形均是在Quartus II软件下得到的。-FPGA traffic lights shows:1procedures for the use of the VHDL sch
startup
- Spartan-3E starter开发板入门例程的重新编译版本，本版本使用最新版ISE14.1重新编译。补充缺少的文件，实际测试通过。-Spartan-3E starter development board entry routine re-compiled version, this version use the latest version ISE14.1 recompile. Added missing files, through the actual test.
SD_Card_Audio
- niosⅡ实现音频的读写的程序，包含整个工程，所有文件不缺失，放心使用，学习的好帮手。-niosⅡ achieve audio literacy programs, including the entire project, all the files are not missing, ease of use, learning a good helper.
cache
- verilog 语言写的一个cache 平台是xillix ISE 实现了从cache中取指令命中和缺失情况的处理 -Verilog language to write a cache Platform is ISE xillix The processing of the instruction hit and the missing the cache is realized.