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  1. tutdac99

    0下载:
  2. Analog and mixed-signal Modeling Using the VHDL-AMS Language
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:408.05kb
    • 提供者:huayuliang
  1. cic18.tar

    0下载:
  2. TAIWAN晶片中心开发的180NM混合信号设计教学库-180nm mixed signal lib for education use from CIC
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:1.05mb
    • 提供者:Alex Xiang
  1. verilog_ams

    0下载:
  2. VERILOG ANALOG mixed signal MODELING TUTORIAL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-25
    • 文件大小:150.8kb
    • 提供者:vijayaragavan
  1. 22222222222

    0下载:
  2. 地址线为8位,数据线为八位的正弦信号发生器,采用文本原理图混合输入的方法。-8-bit address lines, data lines for the eight sinusoidal signal generator, using the text input method for mixed schematic.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-14
    • 文件大小:21.11mb
    • 提供者:高亮
  1. v

    0下载:
  2. vhdl VHDL (VHSIC hardware descr iption language) is a hardware descr iption language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-25
    • 文件大小:226.55kb
    • 提供者:dhaouadi
  1. coding_and_synthesis_with_verilog

    0下载:
  2. In the semiconductor and electronic design industry, Verilog is a hardware descr iption language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verificati
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:28.09kb
    • 提供者:nataraja
  1. vhdlffiltter

    0下载:
  2. 可生成一个正弦信号,并加入白噪声,的到正弦信号和白噪声的混合信号,通过低通滤波器对白噪声进行处理,已通过测试。-Generates a sinusoidal signal, and adding white noise, the sinusoidal signal and white noise to the mixed-signal, white noise through a low pass filter processing, has been tested.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-26
    • 文件大小:65.92kb
    • 提供者:
  1. SMIC180MMRF

    12下载:
  2. 为了提供客户使用中芯国际0.18微米混合信号布局设计规则。这是混合信号和射频设计使用。逻辑设计,请参考2001年TD- LO18- DR。-To provide SMIC 0.18μm mixed signal layout design rules for customers’ use. This is for mixed-signal and RF design use. For Logic design, please refer to TD-LO18-DR-2001.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2015-12-02
    • 文件大小:12.24mb
    • 提供者:pong hk
  1. digital-filter

    0下载:
  2. Verilog语言综合的固定频率的数字滤波器,用于滤除夹杂在固定频率信号上的杂波信号,包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:209.63kb
    • 提供者:张秋光
  1. AMSD_in_GUI.tar

    1下载:
  2. 锁相环(pll)AMS仿真实例,平台为cadence+ius。-tutorial for the simulation of mixed signal pll
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-18
    • 文件大小:4.61mb
    • 提供者:minglinma
  1. Source

    0下载:
  2. This power point file consist of a lot of different vhdl code for component with source code VHDL (VHSIC Hardware Descr iption Language) is a hardware descr iption language used in electronic design automation to describe digital and mixed-signa
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:897.36kb
    • 提供者:pouya
  1. N-DtoA-VHDL-AMS

    0下载:
  2. 下面是一个混合信号的例子,是一个N位D/A转换器的VHDL-AMS描述-The following is an example of a mixed signal that is a N bit D/A converter described in VHDL-AMS
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:6.59kb
    • 提供者:杜子腾
  1. analog_and_mixed_signal_ic_design

    1下载:
  2. 模拟与混合信号集成电路前端设计培训,内含ADC设计,verilog A, SPICE,设计方程\方法等(Analog and mixed signal ic front end design tutorial, example ADC design. including Verilog A, SPICE and design equations for AMS circuit design.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-10-06
    • 文件大小:23.92mb
    • 提供者:Alex Xiang
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