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多功能数字钟，实现了计时、校分、闹钟、日历等功能，已通过仿真验证-Multifunction digital clock, to achieve the timing, the school points, alarm clock, calendar and other functions, has been verified by simulation
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该工程的主要功能是由VHDL语言实现多功能数字电子时钟-The project s main function is to achieve by the VHDL language multifunction digital electronic clock
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多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
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多功能数字钟的VHDL源代码。多功能数字钟具有的功能：显示时－分－秒、整点报时、小时和分钟可调等基本功能。钟表的工作是在1Hz信号的作用下进行，每来一个时钟信号，秒增加1秒，当秒从59秒跳转到00秒时，分钟增加1分，同时当分钟从59分跳转到00分时，小时增加1小时。-Multifunction digital clock VHDL source code. Multi-function digital clock with functions: display- minutes- seconds
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多功能数字钟的设计，可显示时－分－秒、整点报时、小时和分钟可调等基本功能。-Multifunction digital clock designed to display- minutes- seconds, the whole point timekeeping, hours and minutes, adjustable and other basic functions.
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quartus软件环境下采用verilog语言编写的多功能数字钟-quartus software environment using verilog language multifunction digital clock
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Verilog多功能数字时钟，是一个可在开发板上实现的时钟程序,不仅可以做为时钟用,还另外加了个跑秒的功能.-Verilog multifunction digital clock is a clock in the development process to achieve the board, not only can be used as the clock use, but also other added a second run features.
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基于EDA的用VerlogHDL编写的多功能数字闹钟-EDA' s written by VerlogHDL based multifunction digital alarm clock
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EDA课程设计多功能数字时钟的设计程序源码，在Cyclone II上验证成功！-EDA curriculum design process multifunction digital clock source, the Cyclone II verify success!
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基于fapa应用verilog语言实现多功能数字时钟-Verilog language based fapa application multifunction digital clock
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南京理工大学EDA实验多功能数字钟+闹钟+dds+am调幅。-Nanjing University of EDA test multifunction digital clock+ alarm+ dds+ am AM.
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这是多功能数字钟的Verilog源程序，此程序已经编译通过，可以使用-This is a multi-functional digital clock in Verilog source code, this program has been compiled by, you can use
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多功能电子钟，实现自动时钟日历的程序，含有时分秒日月年-Multifunction Clock
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在quartus平台下利用Verilogyu语言编写的多功能数字钟，数字钟有定时、调时、闹钟、秒表等功能-Quartus platform the use of Verilogyu language multifunction digital clock, digital clock timing, tone, alarm clock, stopwatch functions
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基于CPLD实验板的多功能数字钟设计，运用VHDL编写程序-Multifunction digital clock design based on CPLD experimental board, the use of VHDL programming
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QuartusII开发的EDA 采用两个双十进制计数器74390 以及其他部件 组成了具有暂停 清零 调时针 调分针 12 24进制转换 整点报时等功能的多功能数字钟-QuartusII EDA developed using two pairs of decimal counter 74390 as well as other components of tune with the suspension cleared tone hour minute 1224 hex conversion
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多功能数字钟，万年历，可显示时间，年月日，闹钟，功能十分强大，在DE0上通过-Multifunction digital clock, calendar, you can display the time, date, alarm clock, is very powerful in the DE0 by
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FPGA写的多功能数字钟，非常适合初学FPGA的同学，作为参考吧。-FPGA write multifunction digital clock, FPGA is ideal for beginner students, as a reference to it.
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在Quartus II 平台下用verilog语言写的多功能数字钟-In the Quartus II platform with verilog language written multifunction digital clock
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该程序主要是用Verilog HDL语言编写的多功能数字钟，包括校时，调试，整点报时和万年历模块。-The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules.
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