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multiply
- 乘法器的vhdl语言描述.本人调试已经通过
float_data_multiple_use_fixed_
- 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！,a program of float multiply, using 3-stage pipeline technology
MULTI8X8
- 乘法器的硬件快速实现，采用Vhdl语言，对于学习芯片开发的人有用。-multiply is completed by vhdl.
multiplier-accumulator(vhdl)
- 用VHDL语言描述和实现乘法累加器设计,4位的被乘数X和4位的乘数Y输入后，暂存在寄存器4位的寄存器A和B中，寄存器A和B的输出首先相乘，得到8位乘积，该乘积再与8位寄存器C的输出相加，相加结果保存在寄存器C中。寄存器C的输出也是系统输出Z。(原创，里面有乘法部分和累加部分可以单独提出来，很好用) -With the VHDL language to describe the design and realization of multiplier-accumulator, four of
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
code
- This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
add8
- 用VHDL语言实现的八位计数器 可进行简单的加减乘除运算-It is a counting device with eight-bit that could plus ,subtract ,multiply and divide.
multiply
- vhdl语言编写，实现了任意位数的两个数的乘法器-Realize any two-digit number of multiplier
my_func_pkg
- multiply vhdl package code
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
54764716
- 乘法电路，vhdl写的。用于VHDL基础学习-multiply
multiply
- 实验报告中完成以下功能：在maxplus2 环境下，完成4bit × 4bit 运算功能，并模拟显示出相关内容，设计动态扫描显示电路，显示两位字符，以便用在4bit × 4bit运算中。 （附源程序代码）-multiplay under maxplus2，use VHDL
lab3
- VHDL Lab 3 – Arithmetic & State Machines In this lab we will look at arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the require
multiply
- 四位加法器的VHDL代码，实现四位加法器FPGA实现。-Four adder VHDL code to achieve the four adder FPGA.
VHDLbasic_cal
- VHDL的加、减、乘、比较等基本运算的源代码-VHDL add, subtract, multiply, compare the source code of the basic operations
FinalCPU
- 用VHDL语言编写的简单CPU程序,实现了加减乘除和移位功能。-a simple CPU program writen by VHDL language , it realizes the add, subtract, multiply ，divide and shift function.
project
- 采用底层设计懂得乘法累加器一般设计方法，对于VHDL相关应用有一定帮助-Know how to multiply-accumulator general design method, the underlying design VHDL related applications
mac21
- this file is a multiply and accumulate logic built in VHDL platform.-this file is a multiply and accumulate logic built in VHDL platform.
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and