在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

用VHDL编写的oscillograph数字部分源代码，在Altera FPGA上跑通。直接把模拟部分输入输出AD，DA信号接入本模块即可。-Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this modul

verilog语言的数字示波器，包括采样，测频，测幅，显示等！-verilog language, digital oscilloscope, sampling, frequency measurement, the measured rate, display!

a ccd driver code,wirte in verilog,there are some error in the timing analyzer in the report after full compiled ,but the wafes on oscillograph are successful