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RX
- 1路视频光端机的接收端,VHDL源码,使用全FPGA芯片的硬件,内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
TX
- 1路视频光端机的发射端,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
MAIN_TX_V10
- 8路视频光端机的VHDL源码,此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。-8-channel video PDH in VHDL source code
F7-2VT-1DR
- 2路视频光端机的,VHDL源码,使用全FPGA芯片的硬件,内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
XilinxFPGA
- 可以很快学会使用xilinx开发环境ISE,是一个不错的初级入门文件。推荐。-the PDH can easy make u know the sample knowlege on FPGA software ISE.it is worthy reading.