搜索资源列表
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
multier
- 利用图元实现层次化设计,编程完成数字序列的乘积求和-The realization of the use of pixel-level design, programming to complete the product sum of the number of sequences
vga_rgb
- 基于FPGA的实验。编写程序实现VGA彩条显示。像素800x600，刷新频率75Hz，实现8位色的彩条显示-FPGA-based experiment. Programming to achieve color VGA display. Pixel 800x600, refresh rate 75Hz, to achieve 8-bit color display color
VHDL
- 1、 输入信号 clk : 时钟（每个象素点的显示时钟） reset : 复位信号 2、 输出信号 vga_hs_control : 行同步 vga_vs_control : 场同步 vga_read_dispaly : 红 vga_green_dispaly : 绿 vga_blue_dispaly : 蓝 3、 技术参数 clk : 24M hs : 30KHZ vs : 57.14HZ -1, input
vga_demo2
- VGA controller : Genarate a VGA signal from your inout information as color info of each pixel-VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
vga
- VGA显示控制：时序控制+像素点的颜色处理显示十字光标（vorilog）-VGA Display Control: Timing Control+ pixel color processing and display cross cursor (vorilog)
mc_t
- 利用verilog实现H.264中半像素插值功能。30个周期完成一个4x4块儿的横向、纵向和斜向的插值。-Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
mc
- 通过VHDL实现H.264算法中的半像素插值模块。该模块儿可在30个周期内完成一个4x4块的横纵斜插值。-H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
vga_lcd_latest.tar
- vga lcd 控制器 24位VGA控制，支持12位DVI协议-This embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost
rgb_collect
- led DVI 同步显示屏控制系统，RGB数据采集，采用TFP401和TFP410芯片，将程序分区块进行采集，裁剪，并按顺序送到后端，供数据处理，程序中有起始点X，起始点Y，水平裁剪数，垂直裁剪数-LED Module display system,rgb pixel collect and output by pixel area~~
color_vga.tar
- VGA DIsplay control. which reads pixel data stored in coregen on fpga and displays image on monitor using VGA
mkjpeg.tar
- 用FPGA实现的JPEG编码器，可以直接使用，内含完成说明文档，经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • T
XD-D01-20110108
- 压缩感知是近几年比较热门的话题，其中我研究的双像素相机就是基于DMD光调制系统和它-Compressed sensing is more popular in recent years, the topic, which I studied double pixel camera is based on the the DMD light-modulation system and
CD1_PHOTO_ABLUM(1920)
- 基于FPGA的1920像素的图片保存显示，图片保存在记忆卡中-FPGA-based 1920 pixel image retention, images stored on the memory card.
MASTER
- ACCUMILATEUR de 9 pixel d image pour filtre median
ov7670
- OV7670驱动代码（源码） 只为驱动代码，输出为像素点信号，必须有相应的下层模块才能完全完成对摄像头的控制-OV7670 driver code (source) only for the driver code, the output pixel signal, there must be a corresponding lower module to fully complete camera control
VGA3gray
- 基于FPGA的显示器测试图像生成程序，开发平台基于DE2-115，红绿蓝三通道控制像素点的颜色。-FPGA-based image generation display test program, the development platform is based on DE2-115, red, green and blue color channel control pixel.
5.-VGA-Text-mode
- A tile-mapped pixel generation scheme is discussed in Section 13.3. A tile can be considered as a super pixel. Whereas a pixel is defined by a 3-bit word in a bit-mapped scheme, a tile is mapped to a predesigned pattern. One method of constructing
vga
- vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a
Screen-saver
- 设计一个屏幕保护程序，对其编译，仿真，下载。 屏幕保护程序具体要求如下： 1. 使用ISE附件中的CORE Generator在块RAM/ROM中存储一幅图像数据，将此模块作为屏幕保护程序的一部分，存储屏幕保护程序中所用的图像。 2. 当启动程序或者按下btn[3]时，图像显示在其初始位置（C1，R1）处，（C1，R1）为图像左上角像素点初始位置。这里，我们设置的初始位置即为左上角坐标（0,0）处。 3. 按下btn[0]，图像按照设定方式产生动态效果。我们的实验中设计的是按下