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使用 Perl语言 ,采用面向对象的编程 (OOP) 方法 ,讨论了一种 Verilog预处理工具的设计.-Using the Perl language, object-oriented programming (OOP) method, discussed the design of a Verilog preprocessing tool.
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语言：VHDL
功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。
仿真工具：modelsim
综合工具：quartus -Language: VHDL
function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
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运算器实现，运用Veriolog语言，编程实现，无错误，顺利编译，可执行，仿真图正确~-ALU implementation, the use of Veriolog language, programming, error-free, smooth build, executable, simulation plan correctly ~
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VHDL语言很严谨，通过对他的学习，编程思维更严谨！这个是很好的VHDL的总结内容，很好对于初学者！-VHDL language is very precise, through his learning, programming, more rigorous thinking! This is a good summary of the contents of VHDL, very good for beginners!
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实验一：不同设计输入方式比较
实验二：VHDL语言编程—组合逻辑电路设计
实验三：VHDL语言编程—时序逻辑电路设计
指导书内容以及详细的程序-Experiment I: comparison of different input methods designed the second experiment: VHDL language programming- Combinational Logic Circuit Design Experiment III: VHDL langu
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实现开发板上的数码管静态循环显示0~F。通过这个实验，掌握采用Verilog
HDL语言编程实现7段数码管显示译码器的方法。-The digital realization of the development board cycling static display 0 ~ F. Through this experiment, using Verilog HDL language to master programming 7-segment display decoder method
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本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
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verilog语言的全面教程，从基础到深入，可以让初学者快速正握verilog语言的编程。-verilog language, comprehensive tutorials, from basic to in-depth, beginners can quickly grasp verilog language is the programming.
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在QUARtusII 环境下开发 应用VHDL语言编程 编写的时钟程序-QUARtusII environment in the development and application written in VHDL language programming clock program
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FIR滤波器，使用Verilog硬件描述语言进行编程-FIR filter, using the Verilog hardware descr iption language programming
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用VHDL语言编程实现UART，8位数据位，校验位自己可以加！LIBERO仿真正确！-VHDL language programming with UART, 8 data bits, parity bit that they can add! LIBERO simulation correctly!
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我们实验室资料，对于学习FPGA的很有帮助，使用的verilog语言来编程-Our laboratory data, very helpful for learning FPGA, using the verilog language programming
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Actel公司FPGA fusion系列M1AFS600的I2C实验的FPGA程序和keil环境下C语言程序，程序测试通过。-Actel Corporation FPGA fusion experimental series M1AFS600 the I2C FPGA procedures and keil C language programming environment, the program test.
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Actel fusion M1AFS600的LCD实验，基于周立功公司CortexM1开发板，程序包括FPGA源程序和Keil环境下C语言程序，程序测试通过。-Actel fusion M1AFS600 the LCD test, Zhou, who based the company CortexM1 development board, the program includes FPGA source code and Keil C language programming environm
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基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
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在EP2C35上用VHDL语言编程实现的正弦波形发生器-VHDL language used in the EP2C35 programming on the sine wave generator
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该程序是一个简单的电梯控制程序,运用VHDL语言编程,能实现电梯所要的功能并在DE2板上演示-The program is a simple elevator control procedures, the use of VHDL language programming, to achieve the desired function of the elevator and in the DE2 board demo
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特定序列检测器，VHDL语言实现，采用状态机的编程思想，同时程序中的被检测序列可以稍微修改以满足自己的需要-Specific sequence detection, VHDL language, the use of state machine programming ideas, and the program sequence can be detected in the slightly modified to meet their own needs
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Verilog HDL程序设计教程,是非常适合Verilog HDL语言的初学者的入门教程，里面详细介绍了语法、结构等方面。-Verilog HDL programming tutorial, Verilog HDL language is very suitable for beginners introductory tutorial, which introduces grammar, structure, and so on.
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Verilog+HDL程序设计实例详解10-13.rar，是学习velilog语言的好材料-Verilog+ HDL programming examples Detailed 10-13.rar, is a good material for language learning velilog
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