搜索资源列表
一些VHDL源代码
- 内有波形发生器,加法器,经典双进程状态机,伪随机熟产生器,相应加法器的测试向量,16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
rn_gen
- random number generator
fenpin(vhdl)
- 使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供 初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
byvhdstopwatchl
- 1.高精度数字秒表(0.01秒的vhdl语言实现) 2.具有定时,暂停,按键随机存储,翻页回放功能; 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔,可控性高。 5.模块化设计,其中的许多函数可以成为vhdl语言的通用经典例子(包含分频电路设计,动态扫描时钟设计,译码电路设计,存储器设计,存储回放显示设计)-1. High-precision digital stopwatch (0.01 seconds vhdl la
9.3_Pulse_Counter
- 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 9.3.1 脉冲计数器的工作原理 9.3.2 计数模块的设计与实现 9.3.3 parameter的使用方法 9.3.4 repeat循环语句的使用方法 9.3.5 系统函数$random的使用方法 9.3.6 脉冲计数器的Verilog-HDL描述 9.3.7 特定脉冲序列的发生 9.3.8 脉冲计数器的硬件实现 -based on V
VHDL-six
- 用VHDL语言实现六分频,并且已经通过编译和仿真。由此可举一反三,实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
serial_produce
- 设计一个能够自启动的24-1的伪随机码(111101011001000)发生器。 设计一个序列信号发生器,产生一个011100110011序列码。 实现序列1110100。测试序列码波形 个人比较欣赏第二种方法 -to design an 24-1 since the start of the pseudo-random number (111101011001000) generator. Design of a signal sequence generator to pro
sram__
- 静态随机读取存储器行为模型,可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
suij
- 硬件编程实现伪随机交织器和随机交织器,应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
weishujituanfashengqishejishili
- 伪随机图案发生器设计实例,也是可以拿来用的,扩频和跳频通信有用-pseudo-random pattern generator design examples, and can be used with the frequency hopping spread spectrum communication and useful
ram
- RAM, Random-access memory,Verilog code
random data gen(vhdl)
- 任意数据发生器的源代码-arbitrary data source code generator
Pseudo-random-code
- 基于FPGA实现的伪随机序列快速同步.rar
pseudorandom
- 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Verilog_code_for_AWGN.rar
- verilog实现awgn信道噪声的代码,支持可变的信噪比。利用移位寄存器来实现伪随机序列。,verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
rom.rar
- 基于Verilog语言编写的各种只读存储器rom和随机存储器ram,Verilog language based on a variety of read-only memory rom and random access memory ram
lfsr
- 此实验介绍了伪随机序列的产生原理,并用verilog语言将其编码实现,有详细的代码备注-This experiment introduces the principle of pseudo-random sequence and its encoded with the verilog language implementation, a detailed code Notes
gen_displayer
- 基于线性反馈移位寄存器电路,并结合FPGA 的特有结构,一种简捷而又高效的伪随机序列产生方法-The Implementation and Research on Pseudo-Random Number Generators with FPGA
random
- 用简单的线性反馈移位寄存器实现了伪随机数的生成…(The pseudo random number is generated by a simple linear feedback shift register)