搜索资源列表
T2_USB_IN.rar
- usb芯片cy7c68013从fpga中读入数据的演示程序，verilog语言,CY7C68013 chip usb read from the FPGA into the data presentation process, verilog language
DE2_SDCARD
- DE2 开发板上，NIOS编程。对SD卡以及USB的读写操作的实例。我的代码及工程绝对完整！代码其实是Verilog编写的。-DE2 development board, NIOS programming. On the SD card and USB examples of read and write operations. My absolute integrity of code and works! Verilog code is written.
top
- 实用的usb数据读取，实现68013数据读取，硬件实现语言-Practical usb data read, data read to achieve 68,013, the hardware implementation language
spart6_usb_rw_example
- 这是USB芯片CY68013和FPGA互连的读写的实例代码，sparten6是新的FPGA平台，对需要使用新的平台的朋友，有一定的帮助。-This is the USB chip and the FPGA interconnect CY68013 read the example code, sparten6 a new FPGA platform, the platform on the need to use the new friends, have some help.
USB_CY7C68013_Verilog
- 利用verilog语言读写基于CY7C68013A的USB器件，使用，轻松上手。-Use language to read and write verilog CY7C68013A based USB device, use, easy to get started.
usb1_funct_latest.tar
- USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi
01-USB
- usb读取，仅供参考，在实际应用中要更改以下数据。-Read usb data
cy7c68013a_test
- cy7c68013 USB芯片的驱动，采用FPGA读写程序，fpga内部与USB接口的通信-the chip drive cy7c68013 USB FPGA read and write procedures, fpga internal USB interface communication
USB-245BMWR20121211
- 关于用verilog语言进行USB芯片FT245BM读写的代码-The verilog language USB chip FT245BM read and write code
ft2232h_rollback
- FT2232H芯片usb循环读写 verilog 实现, 使用时pll可注释掉-FT2232H the chips usb cycle read and write verilog achieve
EZ_USB_LOOPBACK
- 本程序：EZ-USB在slave fifo模式下，利用FPGA控制EZ-USB的数据读写-This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write
usb1029
- 实现FPGA对Cypress公司的68013A款的USB芯片应用于SLAVEFIFO的读操作，使用verilog语言编写，Q2开发环境。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, using verilog language, Q2 development environment.
wishbone
- Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(
msp430f5529_usb_rw
- 430单片机的USB读写实验，基于msp430f5529开发板，大家可以学习一下-430 singlechip USB read and write test, based on the msp430f5529 development board, you can learn about it
usb_rd_buffer
- FPGA（SPARTAN6）通过USB协议与开发板上的USB芯片进行数据读写测试，在上位机上可以看到USB发来的数据，也可以通过修改VERILOG代码完成数据的接收(FPGA (SPARTAN6) can read and write data through the USB chip on the development board through the USB protocol. The data sent by USB can be seen on the host computer,