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CompilerOptimizations
- To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level o
ALU1
- ALU 指令格式(16位） op DR SR fun 0--3 4—7 8--11 12--15 指令类 OP码 指令 FUN 功能描述 控制 0000 NOP 0000 空指令 HLT 0001 停机 有条件跳转 0010 JZ 0000 Z=1，跳转 JC 0001 C=1，跳转 JNC 0010 C=0，跳转 JNZ 0100 Z=0，跳转 Jump 0101 无条件跳转 LOAD 001
bubblesort1024ram
- 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking trad
EP3C25
- Cyclone® III EP3C25的资料-Cyclone 庐 III EP3C25 information
XilinxISE8
- This tutorial gives a descr iption of the features and additions to Xilinx® ISE™ 8.2i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementatio
cycloneIII3c120dev
- This document describes the hardware features of the Cyclone® III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.-This document describes the ha
LCD
- 基于FPGA_EP2C8的lcd控制器，显示字符，初学者使用-module lcd_driver(clk,rst,LCD_DATA,RS,RW,EN) input clk,rst //rst is the signal of reset,active low(0). output RS,RW,EN //R
shift_reg
- 移位寄存器 移位寄存器 移位寄存器-shift-reg
song
- module song(clk,key,song_out,led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0] delay reg [7:0] key_reg always @(posedge clk) begin count=count+1 if((count==de
3_8CODER
- module decoder_38(out,in) output[7:0] out input[2:0] in reg[7:0] out always @(in)
0514
- 16位4*4寄存器组 可以用于模拟主机系统设计时使用-16B reg
regregreg
- 环境上没有看到verilog，才选VHDL 程序是verilog写的 实现电平敏感的1 位数据锁存器-function to complice reg with verilog
SHIFTREG_TEST
- 此文件为移位计数器的测试文件，用VHDL语言编写。可供参考-SHIFT REG TEST
Altera_Embedded_Peripherals_Handbook
- Altera公司原版资料，嵌入式设备handbook。-The handbook you are holding (the Altera Embedded Peripherals Handbook) describes Intellectual Property (IP) cores provided by Altera® for embedded systems design. The following is true of all cores described in
Profiling_Nios_II_Systems
- Altera公司原版设计手册，nios ii ide profiling模式使用。-This application note describes a variety of ways to measure the performance of a Nios® II system with three tools: the GNU profiler, called nios2-elf-gprof, the timestamp interval timer component,
ug_vip
- Altera公司原版设计手册，关于video and image processing ip-This document describes the Altera® Video and Image Processing Suite collection of IP cores that ease the development of video and image processing designs. You can use the following IP cores i
cyc2_cii5v1_01
- This section provides information for board layout designers to successfully layout their boards for Cyclone® II devices. It contains the required PCB layout guidelines, device pin tables, and package specifications.-This section provides
reg-a-wire
- verilog 使用中reg 与 wire 区别及使用方法-verilog using the difference between reg and wire and method of use
register file generation
- the zip file consist of the verilog code which generate the 32 bit reg file so that u can read and write the data into them
Reg-vs-Wire
- This book explains about difference between REG and WIRE in Verilog.