搜索资源列表
8位相位相加乘法器
- 8位相 加乘法器,具有高速,占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages
sdram
- sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块,而不做SDRAM通用控制器,这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单,没有多余的逻辑资源有利于提高控制器的速度,满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, a
cpldPWM
- verilog HDL 编写的PWM,是初学CPLD者入门Z资源,epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
基于FPGA的直接数字合成器设计
- 1、 利用FLEX10的片内RAM资源,根据DDS原理,设计产生正弦信号的各功能模块和顶层原理图; 2、 利用实验板上的TLC7259转换器,将1中得到的正弦信号,通过D/A转换,通过ME5534滤波后在示波器上观察; 3、 输出波形要求: 在输入时钟频率为16KHz时,输出正弦波分辨率达到1Hz; 在输入时钟频率为4MHz时,输出正弦波分辨率达到256Hz; 4、 通过RS232C通信,实现FPGA和PC机之间串行通信,从而实现用PC机改变频率控制字,实现对输出正弦波频率的控制。-a use
two_d_dct_serial
- altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码,语言是:verilog 性能不错,不过资源消耗有点大,可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be us
终端CPLD逻辑工程文件
- 该工程文件实现ARM系统中CPLD的逻辑工作,起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function
Multiplier.rar
- 乘法器 所占资源很少 很好的一个乘法器 史书上的一个例子 说得很好啊,Multiplier good share of scarce resources in the history books on a multiplier an example of very good
adc0804_new.rar
- AD0804驱动,使用新的查表方式,可大大的降低数值运算,节省CPLD的资源,AD0804 driver,using a new method_look up table,which can save a lot of resources of CPLD
ds18b20
- 单路DS18B20的verilog HDL 代码,精度为1℃无须转换数据,直接输出结果。占用300个LE资源。-Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
ft245
- FT245 fifo 控制器 实现对FT245与FPGA内部资源的数据交互-FT245 FT245 fifo controllers and the FPGA internal resources for data exchange
vliw
- vliw processor core vhdl files compiled by myself partly and through the help of net resources.
FPGAPLL
- FPGA做的PLL 可以使用,比软件自带的省一些资源-PLL can be used FPGA to do more than the software comes with some of the resources of the province,
5SGSD5H3F35C4
- ALTERAL的Stratix5GS系列芯片的电路图、管脚分配、性能手册,方便配置芯片和使用资源-The schematic of ALTERAL the series of Stratix5GS chip, pin allocation, performance manuals, convenient configuration chip and use of resources
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码,输入信号有时钟、时钟使能、复位、给定的卫星编号,输出产生的C/A码。此程序在代码上进行优化,占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
vhd-train
- 这些是FPGA的一写资源,希望对大家有所帮助啊-These are the FPGA resources of a write, I hope all of you to help ah
clock_domain_process
- 一种将异步时钟域转换成同步时钟域的方法,可节省资源,避免格雷码转换。-A will be converted to asynchronous clock domain synchronous clock domain methods, can save resources, and avoid the Gray code conversion.
chengfaqi4
- 用VHDL实现四位乘法器,不直接用乘法实现,一来节省资源,二来可提高速度!-Use VHDL to achieve four multiplier, not the realization of the direct use of multiplication, one to save resources, and secondly to improve the speed!
Clocking-resources-Spartan-6
- CLOCK RESOURCES FOR SPARTAN 6 LX150T.
VHDL-Resources
- 编写VHDL程序与之相关的资源调用与特色电路设计方法,资料中提供了许多案例帮助用户熟练使用VHDL语言设计电路-Write VHDL program associated transfer of resources and characteristics of the circuit design method, the information provided in many cases to help users familiar with the VHDL language circuit
Verilog-hdl-resources
- verilogr的相关教程,比较完整的讲述的verilog 设计的相关知识点-verilog related text resources