搜索资源列表
1.i2c_slave
- I2C的slave端程序,用于响应master端,并进行通信-the slave I2C software, in response to the master terminal, and communications
CommandResponse
- verilog语言写的sdram控制器—命令响应模块代码，经过测试，逻辑正确，可编译，可综合-verilog language written sdram controller-order response to the code, tested, logically correct, compiler, integrated
qiangdaqi
- 使用vhdl语言设计的一个四人参加的智力竞赛抢答计时器。当有某一参赛者首先按下抢答开关时，响应显示灯亮并伴有声响，此时抢答器不再接受其他输入信号。电路具有回答问题时间控制功能。要求回答问题时间小于100s（显示为0—99），时间显示采用倒计时方式。当达到限定时间时，的发出声响以示警告。 -Using VHDL language design four people to participate in the quiz answer in the timer. When a participa
VGA_Ctrl
- 基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态，需要写一个Avalon 从端口响应CPU的控制信号，继而控制整个模块的运行，-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to wri
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!
mtd
- MTD定点浮点仿真，可直接用于fpga算法的仿真程序，产生了扫频信号，仿真直接输出系统频率响应函数，为系统测试带来好处-MTD fixed-point floating-point simulation, fpga algorithm can be used directly in the simulation program to produce a sweep signal, the direct simulation output system frequency response fun
hilbert_transformer_latest.tar
- The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hil
send_cmd
- SD card SDIO module send command and read response
direct_implementation
- VHDL 实现 有限冲击响应滤波器的设计（直接式）-VHDL realization of finite impulse response filter design (direct)
distributed_implementation
- VHDL 实现 有限冲击响应滤波器的设计（分布式）-VHDL realization of finite impulse response filter design (distributed)
serial_implementation
- VHDL 实现 有限冲击响应滤波器的设计（串行式）-VHDL realization of finite impulse response filter design (Serial)
book
- Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware descr iption language, VerilogHDL suitable algorithm level, rtl, logic level, gate-lev
fpga2
- 基于FPGA的有限冲激响应数字滤波器的研究及实现 -FPGA-based Finite Impulse Response digital filter of the research and realized FPGA-based Finite Impulse Response digital filter of the research and realized
ImplementLUT-baseFIRFilterwithVHDL
- 用VHDL语言实现查找表方法有限冲击响应滤波器-VHDL language used lookup table method to achieve finite impulse response filter
ps2.vhd
- vhdl ps2 interface for practical use. please send me a response.
dianti
- 1.每层电梯入口处设有上下请求开关各1个，电梯内设有乘客到达层次的数字开关。电梯当前所在的楼层位置用一位数码管显示，用一只发光二极管显示开门/关门状态，用发光二极管显示每层的上下请求状态； 2.显示电梯当前所处位置和电梯上行下行及开门，关门状态； 3.电梯到达有停靠站请求的楼层后，电梯门就会自动打开门指示灯亮，开门3秒钟后； 4.电梯门自动关闭（开门指示灯灭）电梯继续运行； 5.对电梯开门时间可以提前关门（按关门按钮）； 6.能记忆电梯内外的所有请求信号，并按照电梯运
fir_filter
- 实现滤波器的功能，有限冲激响应（FIR）数字滤波器和无限冲激响应（IIR）数字滤波器广泛应用于数字信号处理系统中。IIR数字滤波器方便简单，但它相位的非线性，要求采用全通网络进行相位校正，且稳定性难以保障。FIR滤波器具有很好的线性相位特性，使得它越来越受到广泛的重视。-Realize the filter function, finite impulse response (FIR) digital filters and infinite impulse response (IIR) dig
2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
VerilogFIR
- low pass FIR filter programmed by Verilog, you can change the coefficients in the program to achieve different response