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vhdl平方根
- 计算某数的平方根，VHDL语言，使用简单-calculate the square root of a number, VHDL, use simple
arith_lib_cadence
- Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
树式除法型开方器VERILOG实现
- 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算,Square root of the tree-type divider-type device to achieve VERILOG
squareroot.rar
- vhdl源代码,可以开16比特的平方根，算法简单，速度快,this is a vhdl code for square root
nios2-flash-override.rar
- 在开发nios2时，当把nios2中写的程序烧录到用epcs4中时会报错，原因是找不到epcs的映射资料，把这个文件，放到quartus根目录的bin文件夹内后，再打开一次flash program，就能下载成功！,Nios2 in the development, when the procedures wrote nios2 writers to use when epcs4 in error, the use of this document, into the root director
470P2F07
- sqrt root using verilog
rrc_filter
- this is a verilog code for root raised cosine filter
sqrt
- 平方根算法的硬件描述语言，算法运行速度快，10位二进制数的开方只需要10个时钟周期-Square root algorithm for hardware descr iption language, the algorithm is fast, 10-bit binary number square root only 10 clock cycles
sqrt
- 实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
SpreadShaping
- 直接序列扩频+成型滤波，将编码后数据进行256倍扩频，再按照4倍内插根升余弦成型滤波，最后成形滤波后按4路并行输出，以满足并行输入DA的要求。-Direct Sequence Spread Spectrum+ shaping filter, the encoded data 256 times more spread spectrum, and then interpolated according to four times the root raised cosine shaping fil
square-root
- Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware descr iption language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation avai
sqrt_for_single_float_point
- 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
A-VHDL-Function-for-finding-SQUARE-ROOT
- vhdl coding for square root-vhdl coding for square root...
33-square-root
- 使用VHDL语言实现33位平方根进位选择加法器，能满足在500M时钟下正确工作，使用DB测试，并通过前仿。-Using VHDL language 33 square root carry select adder, to meet in the 500M clock work correctly, use the DB test, and through imitation.
square-root
- simulink/matlab 实现求实数平方根-using simulink to calulate the sequare root of the integer
Square-Root
- Square Root code in VHDL