搜索资源列表
maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
GF_2_m_FPGA
- GF_2_m_域乘法器的快速设计及FPGA实现，对于rs编翼码的理解和设计有帮助
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
RS
- 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
RS
- RS译码器的设计，使用RS码设计的译码器-RS decoder design, the use of RS code decoder design
RS_encode_and_decode
- 文章详细描述了关于RS码的编码和解码全过程，讲解从浅入深，值得学习参考-The file describe the RS code and decode, there are a lot of examples in it, so you can understand it easily
Trigger
- 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
RS21
- 该源代码是RS（31，19）码的编码程序，采用的是VerilogHDL语言，这是个完整的程序，能够直接在ISE软件上运行-The source code is RS (31,19) code coding procedures, the is VerilogHDL language, which is a complete program can be run directly in the ISE software
RS2
- 该源代码是RS（31，19）码的完整编译码程序，采用的是VerilogHDL语言，包含了RS码的编码和译码，这蛋疼的东西花费好多时间-The source code is RS (31,19) code complete encoding and decoding procedures, and spend a lot of time using is VerilogHDL language contains the encoding and decoding of RS codes, this
rs_decode_31
- RS码的FPGA编码文件，QUARTUS工程-The RS codes FPGA encoded file, QUARTUS engineering
VHDLrsjiemaqi
- 设计中国移动多媒体广播中的RS解码器,该RS码采用码长为240字节的RS(240, K)截短码-RS decoder design in China Mobile Multimedia Broadcasting
(255_223)-RS-decoder
- 使用VHDL实现（255,233）的RS硬件译码器，详细地介绍了(255，223)RS码硬件译码器的实现流程，并且分析了影响处理速率提高的瓶颈因素，采用RiBM算法实现译码-Use VHDL (255,233) RS hardware decoder, a detailed descr iption of the (255,223) RS code hardware decoder implementation process, and analyze the bottleneck factor
encoder
- RS(7,3,4)，码长七位，信息位三位，纠错位四位，经过验证成功-RS (7,3,4), the code length of seven, three of information bits, bit error correction four proven successful
rscode
- R S编 解 码 实 现 代 码 verilog语言-RS CODE AND ENCODE
paobiao
- 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
RSdecoder
- 自己写的基于verilog的RS译码器，能够实现RS(240，224)码译码，一级流水设计，可连续译码也可非连续译码。-RSdecoder for RS(240,224).