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sdram_mdl
- verilog实现SDRAM控制器，quartus工程-verilog SDRAM controller, quartus project
altera_sdram
- 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
Sdram_Control_4Port
- 使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632，经过实验板验证，绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
sdram_mdl
- FPGA控制SDRAM的工程，是用Verilog写的，很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
sdram_me
- 用verilog代码控制sdram,sdram_module是顶层模块。控制8M x 16bits x4Banks sdram. -use verilog program to control the sdram
DE2_70_NIOS_10_flash
- 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdra
LL
- verilog语言描述的SDRAM程序代码。-verilog language to describe the the SDRAM procedure code.
sdram_mdl
- 用Verilog HDL编写的SDRAM控制程序，在DE2-70上测试通过，有很大的参考价值。-SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.
dab1814114c3
- 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Descr iption ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
SDR-SDRAMverilog
- 经典三星SDR SDRAM读写verilog代码分享-Classic Samsung SDR SDRAM read and write verilog code share
Sdram_Control_4Port
- SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve
Sdram_PLL
- SDRAM的锁存器控制程序verilog代码-The SDRAM latches control program verilog code
Sdram_WR_FIFO
- 用SDRAM实现的写堆栈操作的verilog源代码-SDRAM write stack operations Verilog source code
sdram_mdl
- 基于verilog的SDRAM读写控制,源自特权同学-SDRAM controller use to read or write base on verilog，it is from teqian
ddr2_v5
- 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
Sdram_Control_8Port
- 用verilog写的8端口SDRAM模块-8-port SDRAM module