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verilog SDRAM core
- 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
标准SDR SDRAM控制器参考设计_verilog_lattice
- 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
sdr sdram controller
- ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
sdram
- sdram controller.verilog
newsdram
- 8读8写SDRAM verilog 程序
Verilog&Vhdl混语言对SDRAM的控制源代码
- Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Sdram_Control_4Port.Verilog写的sdram的控制器
- 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
SDRAM_VerilogCode.rar
- 基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。,FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.
HY57V641620HG.vp.rar
- Hynix公司8M Byte SDR SDRAM的Verilog语言仿真实现,Hynix' s 8M Byte SDR SDRAM Simulation of the Verilog language
sdram 仿真模型
- sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
SDRAM
- SDRAM的verilog程序，很好地程序，希望大家支持-SDRAM verilog program, a good program, I hope you will support
SDRAM-verilog
- SDRAM控制器.用verilog实现SDRAM的读写操作。-sdram coll
SDRAM controller
- This SDRAM controller is useful for SDR_SDRAM IC's can be integrated with the verilog code. The code is developed for the altera FPGA's and it can be ported to other FPGA's easily. The code is verified with terasic DE2-115 board and DE2 boards.
DDR3-SDRAM-Verilog-Model
- 官方网站的verilog语言描写的ddr3 sdram仿真模型。各种型号可选。
11_ddr3_test
- fpga ddr3 sdram verilog 黑金的板子(fpga ddr3 sdram verilog)
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t
sdr_sdram
- sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
SDRAM
- 基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
sdram
- sdram的驱动开发，支持单字节读写，全页读写，自定义长度读写。(SDRAM drive development, support single byte read and write, full page read and write, custom length read and write.)