搜索资源列表
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
pn_generator.rar
- FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。,FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-
TranslateToUTOPIA
- VHDL写一个转换到utopia接口的转换源程序.可以进行utopia接口的仿真试验-VHDL to write a converter to convert source utopia interface. Can utopia interface simulation test
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
FPGAbasedPCIinterfacedesignanditssimulation
- 基于FPGA的PCI接口设计的源代码以及其仿真测试文件-FPGA-based PCI interface design of the source code and its simulation test file
RD1011_rev01.2
- 采用VHDL实现的UART硬件模块，该模块包括了modem的硬件实现，已经仿真测试代码，顶层模块可以采用VHDL或verilog实现，便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog t
test
- 比较两个数大小的源程序，使用Verilog编写，而且包含了测试代码部分，可用modelsim仿真得到波形-Comparison of two numbers the size of source, using Verilog write, but also contains some test code that can be used to be waveform simulation modelsim
FIR
- FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
Principles_of_Verifiable_RTL_Design
- 本书详细讲解了可验证的RTL级代码的原理，为编写RTL仿真测试程序提供了理论基础-This book gave a detailed RTL-level code verifiable principles for the preparation of RTL simulation test program provides a theoretical basis for
AutoWashing
- 基于verilog-hdl的洗衣机自动控制电路，经下载仿真测试通过 附带时钟分频器-Verilog-hdl-based automatic control circuit of the washing machine, after download the simulation test
Microprogramcontroller
- 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.
manch
- 该文件是一个完整的工程文件，用VerilogHDL语言编写，包括曼彻斯特编码器的设计文件和仿真测试文件以及解码器的设计文件和仿真测试文件。在Modelsim中仿真测试通过。-The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design
microprocessor
- 一个微处理器的Verilog代码，根据英文书籍《数字设计与架构》中的例子而写，能够运行MIPS指令，能正确执行跳转指令。通过modelsim仿真，含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump
chap3
- 一段小小的四位累加器的实现程序，通过仿真测试，免费下载-The realization of a small four accumulator process simulation test, free download
8255compile
- 对8255的三个I/O接口进行单个运行并仿真，测试准确可用，并进行了截图。-Three of the 8255 I/O interface to a single run and simulation, test accuracy available, and were shot.
Wrtingtestbench
- 介绍如何写FPGA的仿真测试程序的书，很实用，容易上手-How to write FPGA simulation test program book, very practical, easy to use