搜索资源列表
SimpleSpi
- master spi的源代码(verilog),包括文档,测试程序-master spi the source code (verilog), including documentation, testing procedures
spi
- SPI总线接口的verilog源码,包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
FPGASPI
- 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
CC2500programmingusingAlteraFPGA
- This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
simple_spi_latest[1].tar
- spi通信,主设备和辅助设备通过spi进行通信,文件中是spi的源代码-spicommunication master and slave is communication.spi is source code
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
spi_master
- 用VHDL编写的一个SPI主机程序,SPI模块采用最常用的模式0方式(即CPOL=0,CPHA=0)通信。文件内含测试文档,已在Modelsim6.5上测试通过,可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
spi_master
- SPI master code: generates CS and tx/rx data
SPI_Master
- 此代码是SPI接口的Master的Verilog源代码,经上板测试是没有问题的,请大家放心使用-This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use
FPGA_SPI_master
- master spi code for quartus
SPI_on-quartus
- spi master code for fpga quartus altera
SPI
- spi master code for fpga quartus altera
SPI-verilog
- spi master code for fpga quartus altera
FPGA_SPI
- 本源码是用verilog语言编写的FPGA的SPI主机代码,可以用做SPI开发参考。-The source code is written in verilog FPGA SPI master code, can be used to develop a reference SPI.
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
SPI-Master
- 有关Verilog的SPI通信的代码,可以应用于FPGA的通信-this is verilog code about SPI
SPI_TEST
- verilog SPI 读写时序,测试验证OK.-SPI Verilog Code, Master and Slaver.
spi_master_module
- Simple VHDL SPI-module core source code (only spi-master)
spi-master
- code for Master side
SPI-Master-master
- Use code for Maser SPI