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s_pandp_s
- 用VHDL编写的并串转换和串并转换实例，希望对您有所帮助，其中输入数据是时钟的16倍-prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock
pn_code
- 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog pro
p2s
- 并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
chuan2
- 用verilog HDL编写的并串转换模块，在ISE软件仿真过，也可综合-Prepared using verilog HDL and string conversion module, in the ISE software simulation, and can also be integrated
alaw
- 使用VHDL实现通信脉冲编码调制（PCM）中的a律转换，并实现串并、并串转换。-Use VHDL to achieve communication pulse code modulation (PCM) of a law conversion, and to achieve and string, and string conversion.
chuanbingzhuanhuan
- 这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的，尤其在通信线路方面的复用和分解方面，原理上就是一个串并转换和并串转换的过程。举个简单的例子，计算机串口发送数据的过程，如果满足发送条件了，其实就是一个并串转换的过程了。好了，废话不说，看代码就是。 -And the string conversion of the code is relying on the synchronization state machine to achieve its c
bingchuan2
- verilogHDL编写的并串转换模块，在ISE软件中仿真过，可综合，绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
bingchuan
- verilogHDL编写的并串转换模块，在ISE软件中仿真过，可综合，绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
rs232
- 串口232程序，实现并串转换及相应的操作-Serial 232 program, to achieve and string conversion and the corresponding operation
p_s
- 用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
shift8
- 用VHDL语言在QUARTUS环境下开发，功能是并串转换移位寄存器-Using VHDL language QUARTUS development environment, and the string conversion function is the shift register
s_p
- 用Verilog HDL语言进行并串转换，并通过Quartus Ⅱ 功能仿真验证-With the Verilog HDL language and string conversion functions through simulation Quartus Ⅱ
SERDES
- 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
SHFRT1_4
- 4位并入串出移位寄存器,实现并串转换,简单易行,通过时序验证.-4-bit shift register into the string out to achieve and string conversion, simple, through sequence verification.
p-to-s
- 采用VHDL语言编制的并串转换程序，大家看看吧-Prepared using VHDL language and string conversion process, we look at it
data_swith
- verilog 代码实现串并转换，有延迟-Verilog code and string conversion, delay
String-and-conversionVERILOG
- 该压缩文件包含一个verilogHDL实现数据的串并连转换功能。-Use verilog realize string and even the conversion function
hc595
- HC595并串转换程序，Verilog语言编写，经过硬件平台测试-HC595 and string conversion process, Verilog language, after testing the hardware platform
p2s
- verilog语言实现的并串转换，适用于quartus环境-the verilog language and string conversion for quartus environment
piso10
- 很有用的10bit并串转换程序，在quartus上已验证过，需要的可以拿去-10bit and useful string conversion process has been verified in quartus need to take to use with