搜索资源列表
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
synth_fft
- 甘地大学电子专业Ray Ranjan Varghese设计的FPGA实现FFT，采用的是单精度的浮点，采用IEEE745格式的浮点+ROM RAM的方式成功实现FFT，含有设计报告和设计源代码，并有测试文件，真的很不错。 -Gandhi University of Electronic Design Professional Ray Ranjan Varghese FPGA realization of FFT, using a single precision floating-point,
P8051
- This a FREE tool chain which compiles C codes into 8051 binary code, converts the binary to RTL ROM, and simulate in Modelsim. SDCC is the compiler. Example compilation: cd compile sdcc --iram-size 0x80 --xram-size 0x800 t8051.c RE
music
- 乐曲硬件演奏电路设计 由顶层文件和数控分频、乐曲简谱码对应的分频预置数查表电路、8位二进制计数器（ROM的地址发生器）组成。演奏乐曲“梁祝”，乐曲可改。已经过硬件下载测试（使用芯片EP1C6Q240 Cyclone系列）-Music by the top hardware performance circuit design file and the NC frequency, music notation code number corresponding to the preset fr
ram-rom-VerilogHDL
- 利用Verilog编写的各种RAM ROM的代码以及他们的测试模块-Prepared using a variety of RAM ROM Verilog code and their test module
mem_test
- ROM存储器的Verilog测试程序，希望对大家有帮助！-ROM memory of the Verilog test program, we want to help!
i2cceshi
- 瑞泰mini光盘下的omap3530的I2C测试，包含头文件，cmd文件等。测试通过。-Skandia mini CD-ROM under the omap3530 the I2C test, include the header file, cmd files. Test.
rom-test
- 简单的FPGA中ROM使用仿真程序，使用的verilog语言-Simple FPGA ROM emulator, using the verilog language
RTL
- verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码，包含测试算法模型，SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model
testrom
- My Uploaded Code to test ROM using VHDL.
ROM_test
- 测试ROM的例子用Verilog写的，里面有测试文件，测试通过完全可用！-Examples of test ROM data
10_rom_test
- rom test,基于FPGA的rom测试，很好的学习资料，大家都来学一学-rom test
test
- 可以产生正弦波，通过ROM，文件中已有完整代码，直接下载即可(Sine wave can be generated through the ROM, the document has complete code, you can download directly)
10_rom_test
- rom ip核的配置，以及测试文件，适合初学者使用。(ROM IP core configuration, as well as test files, suitable for beginners to use.)
ethernet_loopback
- 通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the ne
rom_test
- rom读写实验，实现FPGA内部rom数据存取(rom read and write,this is a good document for study FPGA verilog)
try4
- 利用mif文件生成ROM/RAM，并附带例化程序和测试文件(Using MIF files to generate ROM/RAM with example programs and test files)
test
- 利用xilinx公司开发的vivado平台中的IP核-rom，实现存储(Using IP core -rom in vivado platform developed by Xilinx, storage is implemented.)