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a_vhdl_8253_timer_latest.tar
- 一个用VHDL语言编写的8254定时器。具有一个同步处理器接口比异步的INTEL8254要好-A VHDL 8254 timer，uses a synchronous (Wishbone) processor interface, rather than an asynchronous of the Intel 8254.
Timer
- 假定系统时钟为50MHz，试设计一个电子秒表电路，使其按0.01s 的步长进行计时。该电子秒表具有异步清零和启动/停止计数功能，最大能计到59.99s，并用数码管显示计数值。用发光二极管显示向分钟的进位信号。-Assume that the system clock to 50MHz, the design of an electronic stopwatch test circuit, so the step by 0.01s to time. The electronic stopwatch
TIMER
- 介绍QuartusII 的TIMER的一些基本情况-Introduction QuartusII' s some basic information TIMER
led
- 定时器中断的例程，实现一秒定时，并在led灯上显示- Writes routine which a timer interrupts, realizes one second fixed time, and demonstrated on the led lamp
VHDL-0.1s-Timer
- 该程序完成了在altera de2 环境下实现0.1s新型计时器，该计时器可以运用于广大体育赛事中，有开关、暂停开始键、复位键。-The program completed the implementation in altera de2 0.1s under the new timer, which can be applied to the majority of sports events, a switch, pause start button, reset button.
0.01s-Timer-designed-in-VHDL
- 该设计方案是用VHDL语言实现0.01s计时器，该方案列出了详细的开发过程和所有源代码，并虽有仿真结果-The design solution is to use VHDL language 0.01s timer, the program lists the detailed development process, and all source code, and although the simulation results
Timer
- 计时器的设计，在Quartus II上运行通过，FOR NJU Cser。使用了signaltap-The design of the timer, run by the Quartus II, FOR NJU Cser. Used signaltap
Timer
- 嵌入式系统的单片集成定时器的Verilog实现。可实现多种配置模式，可作为通用的定时器设计模板-This is a standed timer for an SOC design.It can realize multible function need to design an micro process circut
any-timer
- 有24/60进制的计时功能，又扩展到可以设计成任意进制计时器，简单实用-A 24/60 hex timing function, but also extended to the timer can be designed into any band, simple and practical
reaction-timer
- reaction timer by verilog
timer
- 基于vhdl的单片机最小系统定时器模块。Timer模块-Timer Module
timer-pwm
- 基于dspic30f2010芯片的定时器模块以及输出比较模块产生可调PWM波C程序源代码-Chip timer module based dspic30f2010 and adjustable output compare module PWM wave generated C source code
TIMER
- SOPC 系统集成编译的TIMER IP核 Verilog代码-timer ip core in SOPC
timer
- nios ii中时钟的测试程序。。求成全-something about timer
4-BIT-TIMER
- VHDL code for four bit timer using J-K Flip flop
Timer
- 這是時間計數器,名字為Timer.rar,功能為電子時鐘的顯示,可分為時分秒。-This is time counter the name Timer.rar, the function of the electronic clock display can be divided into minutes and seconds.
counter-interrupt-8-timer-04s
- 单片机源程序（keilC语言）---计数器中断8次定时04s件，不需编程，但仅是对霍尔传感器测速应用的验证。-SCM source (keilC language)--- counter interrupt 8 timer 04s
timer
- VHDL 实现定时器 嵌入式单片机 编程-VHDL Timer embedded microcontroller programming
clocker-and-timer
- 时钟与计时器，FPGA实验alter DE2开发板自带光盘的案例教程编程解析-Clock and timer, FPGA experimental alter the DE2 development board comes with the CD case tutorial programming resolution
timer
- 在nios环境下，结合verilog语言开发，功能是结合系统定时器的流水灯操作-Nios environment, combined with the verilog language development is a combination of water of the system timer lamp operating